The design implements a single-cycle RISC-V processor, according to the Hennessy-Patterson architecture. The design consists of an Instruction Memory, an Instruction Decoder, a Register File (32x64-bit wide) , a ALU (arithmetic logic unit) and a Data Memory.
To operate an the registers of the register file, a arithmetic logic unit (ALU) is needed. In this design, a simple integer ALU is used. The ALU takes two 64Bit inputs and calculates a third 64Bit wide output. The operation of the ALU is controlled by two control signals, which are generated in the instruction decoder.
The Instruction decoder is the main control unit of the RISC-V design. It is responsible for generating all control signals and decomposing the instructions from the instruction memory. Also the control signals for the ALU are generated by the instruction decoder. The Instruction decoder implemented in this project consists of a control unit block, an imme�diate extension unit, and a program counter. The control unit block is responsible for generating control signals for both data memory and instruction memory. Additionally, it provides a 3-bit wide control signal to the ALU, which determines the specific operation to be performed by the ALU.
The architecture of the register file accords to the Hennessy-Patterson architecture. the register file is a datapath element to store data in 32 64bit wide registers. The register file can be read
and written by supplying a address to the address input. To operate different formats of instructions, data has to be read and written simultaneous. An R-Type instruction like add has to read two
source operands from the register file and write one value back (destination operand). The address width is 5Bit to address the 32 registers.
The Instruction and Data memory is separated from the processor itself.
