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Improvements and fixes for AMD SOF stack #4500
Improvements and fixes for AMD SOF stack #4500
Commits on Aug 1, 2023
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ASoC: SOF: amd: remove unused sha dma interrupt code
During initial development time for RN platform, when SHA dma gets completed, SHA DMA engine used to raise the ACP interrupt. In ACP interrupt handler, SHA DMA interrupt got handled. Currently SHA DMA compleition is verified by checking transfer count using read poll time out logic. Remove unused SHA dma interrupt handling code. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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ASoC: SOF: amd: enable ACP external global interrupt
Previously ACP SOF firmware used to enable the ACP external global interrupt register. This will restrict to report ACP host interrupts only after firmware loading is successful. This register needs to be set from host driver to handle other ACP interrupts(SoundWire Interrupts) before loading the ACP firmware. Add field for external interrupt enable register in acp descriptor structure and enable the external interrupt enable register. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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ASoC: SOF: amd: add module parameter for firmware debug
Add module parameter for firmware debug. If firmware debug flag is enabled, clear the fusion stall bit which is required for enabling firmware debugging through JTAG. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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Commits on Aug 4, 2023
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ASoC: SOF: amd: remove redundant clock mux selection register write
ACP clock mux selection register is already programmed during acp init sequence. Remove the redundant register write. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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ASoC: SOF: amd: add conditional check for acp_clkmux_sel register
Few AMD platforms require ACP ACLK as clock source. Add conditional check for clock mux selection register for switching between internal clock and ACP ACLK. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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ASoC: SOF: amd: clear panic mask status when panic occurs
Due to scratch memory persistence, Once the DSP panic is reported, need to clear the panic mask after handling DSP panic. Otherwise, It results in DSP panic on next reboot. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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ASoC: SOF: amd: clear dsp to host interrupt status
DSP_SW_INTR_STAT_OFFSET is a common interrupt register which will be accessed by both ACP firmware and driver. This register contains register bits corresponds to host to dsp interrupts and vice versa. when dsp to host interrupt is reported, only clear dsp to host interrupt bit in DSP_SW_INTR_STAT_OFFSET. Fixes: 2e7c665 ("ASoC: SOF: amd: Fix for handling spurious interrupts from DSP") Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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