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[DNM] intel_adsp: ace: dynamic clock switching #8423

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[DNM] intel_adsp: ace: dynamic clock switching #8423

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5183a8b
[DRAFT] west.yml: zephyr version update
tmleman Oct 31, 2023
1fe1d9a
config: ace: enable ARCH_CPU_IDLE_CUSTOM
tmleman Dec 21, 2023
08a4a94
zephyr: pm_runtime: integrate dynamic clock switching support
tmleman Dec 22, 2023
a17cd0f
ipc4: handler: stabilize clock during delayed ipc reply
tmleman Dec 22, 2023
2a46303
ipc4: restore DSP clock on ipc message receipt
tmleman Dec 22, 2023
b005224
zephyr: ll-schedule: restore clock after idle in scheduler
tmleman Dec 22, 2023
c11531b
config: ace: enable dynamic clock switching
tmleman Dec 22, 2023
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4 changes: 4 additions & 0 deletions src/ipc/ipc4/handler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -536,16 +536,20 @@ static int ipc_wait_for_compound_msg(void)
{
int try_count = 30;
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Could we generalize this a bit? I guess this could be a Kconfig to "keep core clock high when responding to IPC".
The actual implementation will vary on different platforms, so ideally we'd have a Zephyr interface to communicate this constraints, but for the time being we might need glue code on SOF side (e.g. for Intel this is turned into pm_runtime call on CORE_HP_CLK).

I'm ok to also go with a TODO comment for now if there's no direct Zephyr interface yet.


pm_runtime_disable(CORE_HP_CLK, PLATFORM_PRIMARY_CORE_ID);
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Is this still needed? Will this work correctly with KCPS which changes clock during IPC?

while (atomic_read(&msg_data.delayed_reply)) {
/* preventing clock switching in idle */
k_sleep(Z_TIMEOUT_US(250));

if (!try_count--) {
atomic_set(&msg_data.delayed_reply, 0);
ipc_cmd_err(&ipc_tr, "ipc4: failed to wait schedule thread");
pm_runtime_enable(CORE_HP_CLK, PLATFORM_PRIMARY_CORE_ID);
return IPC4_FAILURE;
}
}

pm_runtime_enable(CORE_HP_CLK, PLATFORM_PRIMARY_CORE_ID);
return IPC4_SUCCESS;
}

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