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intel_adsp: ace: enable clock gating #8597

Merged
merged 2 commits into from
Dec 15, 2023
Merged

intel_adsp: ace: enable clock gating #8597

merged 2 commits into from
Dec 15, 2023

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tmleman
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@tmleman tmleman commented Dec 8, 2023 •
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Zephyr version update + enabling of the clock gating in ACE platforms

lgirdwood
lgirdwood reviewed Dec 11, 2023
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LGTM

@tmleman
west.yml: update zephyr to 0a7251e365a
f56f455 
Total of 74 commits.

Changes include:

0a7251e365a xtensa: mmu: Fix tlb shootdown
a19d415c350 xtensa: mmu: Fix xtensa_ptevaddr_get
7382d7052b5 xtensa: mmu: Fix partition permission
b5ca7a06b43 pm: device_runtime: Add delay to async put
0ea173b7747 pm: device_runtime: Avoid unnecessary resume/suspend
3732aae0e07 intel_adsp: power: clock gating in idle
9d1a6b6db5a arch: xtensa: rename expection header

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
@tmleman
config: ace: enable clock gating
799ff7a 
This patch enables clock gating in configurations of a ace platforms.

With CONFIG_ADSP_IDLE_CLOCK_GATING enabled clock gating is always
enabled during WAITI.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
@tmleman tmleman force-pushed the topic/upstream/pr/ace/power/clock_gating branch from 32f1ec0 to 799ff7a Compare December 12, 2023 10:57
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tmleman commented Dec 12, 2023

codestyle/checkpatch reports a problem only to the word used in the commit title in zephyr.

@tmleman tmleman marked this pull request as ready for review December 12, 2023 11:34
@kv2019i
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kv2019i commented Dec 12, 2023

Ready to go, but need to analyze why Intel System/merge/build CI step failed.

@abonislawski
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Please verify this failing test before merge

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kv2019i commented Dec 14, 2023

I can see @tmleman you triggered a new build. Let's see the results. Looking at the previous run, there seems to be this:

[    4.178738] <err> zephyr: cpu_disable_core: core 1 did not enter idle state
[    4.178745] <err> ipc: ipc4_module_process_dx: failed to disable core 1
[    4.178748] <err> ipc: ipc_cmd: ipc4: MODULE_MSG failed with err 6

This seems like a case of #8588 so not specific to this PR necessarily.

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tmleman commented Dec 14, 2023

@kv2019i Yes, previous Fail seems to be not related to the enabling of the clock gating. I wasn't able to reproduce it locally and CI test rerun shows that it has sporadic nature.

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kv2019i commented Dec 15, 2023

Need to check the one fail in https://sof-ci.01.org/sofpr/PR8597/build1037/devicetest/index.html to see if it's a known thing, otherwise this looks good to go.

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kv2019i commented Dec 15, 2023

@kv2019i wrote:

Need to check the one fail in https://sof-ci.01.org/sofpr/PR8597/build1037/devicetest/index.html to see if it's a known thing, otherwise this looks good to go.

So that seems to be a case of 8510. No DSP or kernel error, but no data received in user-space in one case (and on a secondary core, like 8510). So I'll proceed with merge.

@kv2019i kv2019i merged commit ddf70fa into thesofproject:main Dec 15, 2023
41 of 44 checks passed
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@tmleman @kv2019i @abonislawski @lgirdwood @btian1 @dnikodem @jxstelter @softwarecki