OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Learn, share and collaborate on ASIC design using open tools and technologies

PLL configuration generator for the Caravel management core

One-button Heroku deploy for the Caravel data exploration platform.

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

An example project that utilizes caravel user space for an ibex based SoC

Eight different verilog projects are combined to creat a big custom asic project.

Sample application for CND(Cloud Native Developer) Livefire Caravel Lab

An ASIC running Pong.

A PCB created for FABulous FPGAs, based on the caravel board.

Druid(v0.8.3) Docker Image(with druid-datasketches extension and caravel included) — Edit