picorv32
Here are 23 public repositories matching this topic...
Physical Design Flow from RTL to GDS using Opensource tools.
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Nov 23, 2020
This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog an…
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Dec 12, 2021 - Verilog
A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
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Oct 3, 2023 - Verilog
A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)
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Jan 18, 2021 - Verilog
5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD
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Oct 18, 2023 - Verilog
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