OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
Oct 20, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
2 Stage OPAM with Miller compensation using Skywater 130nm
A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
Fully-differential asynchronous non-binary 12-bit SAR-ADC
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
Standard cells for SKY90FD provided by SkyWater.
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