drivers: irqsteer: adjust CHn_MASK index computation #394
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dbaluta
approved these changes
Oct 18, 2024
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Tested with SOF on i.MX8QM/8QXP/8MP. Works fine. |
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There needs to be a Zephyr side manifest PR that references this HAL PR |
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@dleach02 zephyr side manifest PR done. |
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Changes since v1:
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dbaluta
approved these changes
Oct 25, 2024
3 tasks
For IRQ_STEER, lower CHn_MASK register indexes are used
to mask higher interrupt IDs. For instance, in the case
of i.MX8MP, the mapping is as follows:
CHn_MASK4 => masks interrupts [31:0]
CHn_MASK3 => masks interrupts [63:32]
CHn_MASK2 => masks interrupts [95:64]
CHn_MASK1 => masks interrupts [127:96]
CHn_MASK0 => masks interrupts [159:128]
The `IRQSTEER_GetRegIndex()` function is used to fetch
the CHn_MASK register index based on a given slice. The term
"slice" is used to refer to an index of a CHn_MASK register in
the set of CHn_MASK registers assigned to a certain master. Assuming
the following partition scheme (i.MX8MP):
{ CHn_MASK4 } is assigned to MASTER0
{ CHn_MASK3, CHn_MASK2 } is assigned to MASTER1
{ CHn_MASK1, CHn_MASK0 } is assiged to MASTER2
CHn_MASK3 would be at slice (index) 0, CHn_MASK2 would be at
slice 1, CHn_MASK1 would be at slice 0 and so on.
To compute the CHn_MASK register index found at a given slice,
`IRQSTEER_GetRegIndex()` uses a base index, which is either
the lowest or the highest CHn_MASK register index in a master's
partition (for instance, for MASTER1 the higher would be 3 and
the lowest would be 2).
For IRQ_STEER instances with an uneven number of CHn_MASK registers
the base is the lowest index, while in the case of instances with
an even number of CHn_MASK registers it's exactly the opposite. This
is an issue because the software using this function might expect
the base to either be the lowest or the highest index ALL THE TIME
(since this affects the order in which the CHn_MASK register indexes
are returned).
As such, fix this problem by making the base the highest CHn_MASK
register index.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
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Has this change been submitted to the SDK team? Please also update the README file to track this change on our end. |
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@LaurentiuM1234, can you update the README file so we can keep track of this change while the SDK team reviews this change. |
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@mmahadevan108 I will update the README file and discuss with SDK team. |
Following patch from MCUX-SDK have been pulled in so update the patch list: - drivers: irqsteer: adjust CHn_MASK index computation Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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@mmahadevan108 all done. Updated README file. |
mmahadevan108
approved these changes
Nov 5, 2024
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For IRQ_STEER, lower CHn_MASK register indexes are used to mask higher interrupt IDs. For instance, in the case of i.MX8MP, the mapping is as follows:
The
IRQSTEER_GetRegIndex()function is used to fetch the CHn_MASK register index based on a given slice. The term "slice" is used to refer to an index of a CHn_MASK register in the set of CHn_MASK registers assigned to a certain master. Assuming the following partition scheme (i.MX8MP):CHn_MASK3 would be at slice (index) 0, CHn_MASK2 would be at slice 1, CHn_MASK1 would be at slice 0 and so on.
To compute the CHn_MASK register index found at a given slice,
IRQSTEER_GetRegIndex()uses a base index, which is either the lowest or the highest CHn_MASK register index in a master's partition (for instance, for MASTER1 the higher would be 3 and the lowest would be 2).For IRQ_STEER instances with an uneven number of CHn_MASK registers the base is the lowest index, while in the case of instances with an even number of CHn_MASK registers it's exactly the opposite. This is an issue because the software using this function might expect the base to either be the lowest or the highest index ALL THE TIME (since this affects the order in which the CHn_MASK register indexes are returned).
As such, fix this problem by making the base the highest CHn_MASK register index.