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dts: nxp: nxp_imx: rt500: update pinctrl files #439

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dts: nxp: nxp_imx: rt500: update pinctrl files #439

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10 changes: 8 additions & 2 deletions dts/nxp/nxp_imx/rt/MIMXRT595SFAWC-pinctrl.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/*
* NOTE: File generated by lpc_cfg_utils.py
* NOTE: File generated by gen_soc_headers.py
* from MIMXRT595SFAWC/signal_configuration.xml
*
* Copyright (c) 2022, NXP
* Copyright 2022, 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/

Expand Down Expand Up @@ -491,6 +491,7 @@
#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */
#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */
#define FLEXIO0_TRIG0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */
#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
Expand Down Expand Up @@ -605,6 +606,7 @@
#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */
#define FLEXIO0_TRIG1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */
#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
Expand Down Expand Up @@ -1218,6 +1220,7 @@
#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */
#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */
#define FLEXIO0_TRIG2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */
#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
Expand Down Expand Up @@ -1332,6 +1335,7 @@
#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */
#define FLEXIO0_TRIG3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */
#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
Expand Down Expand Up @@ -4752,6 +4756,7 @@
#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define FLEXIO0_TRIG1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */
#define PIN_32KHZ_CLKOUT_PIO2_14 IOPCTL_MUX(78, 7) /* PIO2_14 */
#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */
Expand Down Expand Up @@ -4864,6 +4869,7 @@
#define GPIO_PIO428_PIO4_28 IOPCTL_MUX(156, 0) /* PIO4_28 */
#define LCDIF_dbi_data1_PIO4_28 IOPCTL_MUX(156, 2) /* PIO4_28 */
#define LCDIF_lcdif_data1_PIO4_28 IOPCTL_MUX(156, 1) /* PIO4_28 */
#define FC12_SCK_PIO4_29 IOPCTL_MUX(157, 6) /* PIO4_29 */
#define FLEXIO0_IO9_PIO4_29 IOPCTL_MUX(157, 8) /* PIO4_29 */
#define GPIO_PIO429_PIO4_29 IOPCTL_MUX(157, 0) /* PIO4_29 */
#define LCDIF_dbi_data2_PIO4_29 IOPCTL_MUX(157, 2) /* PIO4_29 */
Expand Down
12 changes: 10 additions & 2 deletions dts/nxp/nxp_imx/rt/MIMXRT595SFFOC-pinctrl.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/*
* NOTE: File generated by lpc_cfg_utils.py
* NOTE: File generated by gen_soc_headers.py
* from MIMXRT595SFFOC/signal_configuration.xml
*
* Copyright (c) 2022, NXP
* Copyright 2022, 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/

Expand Down Expand Up @@ -493,6 +493,7 @@
#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */
#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */
#define FLEXIO0_TRIG0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */
#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */
Expand Down Expand Up @@ -607,6 +608,7 @@
#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */
#define FLEXIO0_TRIG1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */
#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */
Expand Down Expand Up @@ -1220,6 +1222,7 @@
#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */
#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */
#define FLEXIO0_TRIG2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */
#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */
Expand Down Expand Up @@ -1334,6 +1337,7 @@
#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */
#define FLEXIO0_TRIG3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */
#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */
Expand Down Expand Up @@ -5513,6 +5517,7 @@
#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define FLEXIO0_TRIG1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */
#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */
#define PIN_32KHZ_CLKOUT_PIO2_14 IOPCTL_MUX(78, 7) /* PIO2_14 */
#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */
Expand Down Expand Up @@ -5634,6 +5639,7 @@
#define CTIMER4_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */
#define CTIMER4_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */
#define FC10_RTS_SCL_SSELN1_PIO3_12 IOPCTL_MUX(108, 6) /* PIO3_12 */
#define FLEXIO0_TRIG0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */
#define GPIO_PIO312_PIO3_12 IOPCTL_MUX(108, 0) /* PIO3_12 */
#define LCDIF_lcdif_data13_PIO3_12 IOPCTL_MUX(108, 2) /* PIO3_12 */
#define USDHC1_USDHC_DATA2_PIO3_12 IOPCTL_MUX(108, 1) /* PIO3_12 */
Expand All @@ -5658,6 +5664,7 @@
#define CTIMER4_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */
#define CTIMER4_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */
#define FC10_SSELN2_PIO3_13 IOPCTL_MUX(109, 6) /* PIO3_13 */
#define FLEXIO0_TRIG1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */
#define GPIO_PIO313_PIO3_13 IOPCTL_MUX(109, 0) /* PIO3_13 */
#define LCDIF_lcdif_data14_PIO3_13 IOPCTL_MUX(109, 2) /* PIO3_13 */
#define USDHC1_USDHC_DATA3_PIO3_13 IOPCTL_MUX(109, 1) /* PIO3_13 */
Expand Down Expand Up @@ -5821,6 +5828,7 @@
#define GPIO_PIO428_PIO4_28 IOPCTL_MUX(156, 0) /* PIO4_28 */
#define LCDIF_dbi_data1_PIO4_28 IOPCTL_MUX(156, 2) /* PIO4_28 */
#define LCDIF_lcdif_data1_PIO4_28 IOPCTL_MUX(156, 1) /* PIO4_28 */
#define FC12_SCK_PIO4_29 IOPCTL_MUX(157, 6) /* PIO4_29 */
#define FLEXIO0_IO9_PIO4_29 IOPCTL_MUX(157, 8) /* PIO4_29 */
#define GPIO_PIO429_PIO4_29 IOPCTL_MUX(157, 0) /* PIO4_29 */
#define LCDIF_dbi_data2_PIO4_29 IOPCTL_MUX(157, 2) /* PIO4_29 */
Expand Down