Process completed with exit code 2.

See https://docs.zephyrproject.org/latest/contribute/guidelines.html#commit-guidelines for more details Commit 375d4e6975: 1: UC5 Commit title exceeds max length (78>75): "tests: thread_runtime_stats: Do not run the test on virtual Cortex-R8 platform"

Process completed with exit code 1.

See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details. You may want to run clang-format on this change: -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +#define MPUTYPE_READ_ONLY \ + {.rasr = (P_RO_U_RO_Msk | (7 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk | \ + MPU_RASR_XN_Msk)} -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } +#define MPUTYPE_READ_ONLY_PRIV {.rasr = (P_RO_U_RO_Msk | (5 << MPU_RASR_TEX_Pos) | MPU_RASR_B_Msk)} -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +#define MPUTYPE_PRIV_WBWACACHE_XN \ + {.rasr = (P_RW_U_NA_Msk | (5 << MPU_RASR_TEX_Pos) | MPU_RASR_B_Msk | MPU_RASR_XN_Msk)} -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } +#define MPUTYPE_PRIV_DEVICE {.rasr = (P_RW_U_NA_Msk | (2 << MPU_RASR_TEX_Pos))} extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), + MPU_REGION_ENTRY("FLASH0", 0xc0000000, REGION_32M, MPUTYPE_READ_ONLY), - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), + MPU_REGION_ENTRY("SRAM_PRIV", 0x00000000, REGION_2G, MPUTYPE_PRIV_WBWACACHE_XN), - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), + MPU_REGION_ENTRY("SRAM", 0x00000000, ((uint32_t)&_image_rom_end_order), + MPUTYPE_READ_ONLY_PRIV), - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + MPU_REGION_ENTRY("REGISTERS", 0xf8000000, REGION_128M, MPUTYPE_PRIV_DEVICE), File:soc/renode/cortex_r8_virtual/arm_mpu_regions.c Line:61 You may want to run clang-format on this change: -#define __CR_REV 1U +#define __CR_REV 1U -#define __GIC_PRESENT 0U -#define __TIM_PRESENT 0U +#define __GIC_PRESENT 0U +#define __TIM_PRESENT 0U File:soc/renode/cortex_r8_virtual/soc.h Line:15 You may want to run clang-format on this change: -#if (defined(CONFIG_SOC_SERIES_MPS2) && defined(CONFIG_QEMU_TARGET)) || \ - (defined(CONFIG_SOC_SERIES_MPS3) && defined(CONFIG_QEMU_TARGET)) || \ - defined(CONFIG_BOARD_QEMU_CORTEX_A53) || defined(CONFIG_SOC_QEMU_ARC) || \ - defined(CONFIG_SOC_CORTEX_R8_VIRTUAL) || \ - defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || \ - defined(CONFIG_BOARD_QEMU_CORTEX_R5) || \ - defined(CONFIG_ARMV8_R) || defined(CONFIG_AARCH32_ARMV8_R) || \ - defined(CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A) || \ +#if (defined(CONFIG_SOC_SERIES_MPS2) && defined(CONFIG_QEMU_TARGET)) || \ + (defined(CONFIG_SOC_SERIES_MPS3) && defined(CONFIG_QEMU_TARGET)) || \ + defined(CONFIG_BOARD_QEMU_CORTEX_A53) || defined(CONFIG_SOC_QEMU_ARC) || \ + defined(CONFIG_SOC_CORTEX_R8_VIRTUAL) || defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || \ + defined(CONFIG_BOARD_QEMU_CORTEX_R5) || defined(CONFIG_ARMV8_R) || \ + defined(CONFIG_AARCH32_ARMV8_R) || defined(CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A) || \ File:tests/ztest/error_hook/src/main.c Line:129

soc/renode/cortex_r8_virtual/arm_mpu_regions.c:61 -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +#define MPUTYPE_READ_ONLY \ + {.rasr = (P_RO_U_RO_Msk | (7 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk | \ + MPU_RASR_XN_Msk)} -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } +#define MPUTYPE_READ_ONLY_PRIV {.rasr = (P_RO_U_RO_Msk | (5 << MPU_RASR_TEX_Pos) | MPU_RASR_B_Msk)} -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +#define MPUTYPE_PRIV_WBWACACHE_XN \ + {.rasr = (P_RW_U_NA_Msk | (5 << MPU_RASR_TEX_Pos) | MPU_RASR_B_Msk | MPU_RASR_XN_Msk)} -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } +#define MPUTYPE_PRIV_DEVICE {.rasr = (P_RW_U_NA_Msk | (2 << MPU_RASR_TEX_Pos))} extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), + MPU_REGION_ENTRY("FLASH0", 0xc0000000, REGION_32M, MPUTYPE_READ_ONLY), - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), + MPU_REGION_ENTRY("SRAM_PRIV", 0x00000000, REGION_2G, MPUTYPE_PRIV_WBWACACHE_XN), - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), + MPU_REGION_ENTRY("SRAM", 0x00000000, ((uint32_t)&_image_rom_end_order), + MPUTYPE_READ_ONLY_PRIV), - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + MPU_REGION_ENTRY("REGISTERS", 0xf8000000, REGION_128M, MPUTYPE_PRIV_DEVICE),

soc/renode/cortex_r8_virtual/soc.h:15 -#define __CR_REV 1U +#define __CR_REV 1U -#define __GIC_PRESENT 0U -#define __TIM_PRESENT 0U +#define __GIC_PRESENT 0U +#define __TIM_PRESENT 0U