boards: openhwgroup: add CVA6 on GenesysII board

Adds support for the CVA6 CPU on a GenesysII FPGA board
(https://github.com/openhwgroup/cva6).
The SoC currently contains the CVA6 CPU  with the SV39 MMU, interrupt
controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot
ROM, and I2C controller for on-board audio, a GPIO and the lowRISC
ethernet subsystem.
Two slightly different versions of the board are added, with a 64-bit
and a 64-bit configuration of CVA6, respectively.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

boards/openhwgroup/cv32a6_genesysII/Kconfig.cv32a6_genesysII

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV32A6_GENESYSII
+	select SOC_CV32A6
+	select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF

boards/openhwgroup/cv32a6_genesysII/board.cmake

@@ -0,0 +1,8 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
+board_runner_args(openocd "--use-elf")
+board_runner_args(openocd "--verify")
+board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/openhwgroup/cv32a6_genesysII/board.yml

@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv32a6_genesysII
+  vendor: openhwgroup
+  socs:
+    - name: cv32a6

boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII.dts

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <openhwgroup/cv32a6.dtsi>
+
+/ {
+	model = "Openhardwaregroup CV32A6 on Genesys II";
+	compatible = "ariane,cv32a6_genesysII";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &memory0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <1 4>;
+};
+
+&spi0 {
+	status = "okay";
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <2 2>;
+};
+
+&clint{
+	status = "okay";
+};
+
+&dma0 {
+	status = "disabled";
+};
+
+
+&mdio0{
+	status = "disabled";
+};
+
+&eth0 {
+	status = "disabled";
+};
+
+&eth {
+	status = "okay";
+};
+
+&xlnx_gpio {
+	status = "okay";
+};

boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII_defconfig

@@ -0,0 +1,40 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+CONFIG_CONSOLE_HANDLER=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000
+CONFIG_FPU=y
+CONFIG_POWEROFF=y
+
+# RNG
+CONFIG_TIMER_RANDOM_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+
+# IRQs
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+# 1 PLIC
+CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
+CONFIG_PLIC=y
+CONFIG_3RD_LEVEL_INTERRUPTS=n
+
+# no networking support on this board
+
+# logging
+CONFIG_LOG=y
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_THREAD_NAME=y
+
+# increased stack sizes
+CONFIG_ISR_STACK_SIZE=524288
+CONFIG_MAIN_STACK_SIZE=524288
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288
+CONFIG_IDLE_STACK_SIZE=524288

boards/openhwgroup/cv32a6_genesysII/doc/index.rst

@@ -0,0 +1,87 @@
+.. _cv32a6_genesys2:
+
+Digilent GenesysII with CV32A6 SoC
+##################################
+
+Overview
+********
+
+The Digilent GenesysII board features a Xilinx Kintex-7 FPGA which can run various softcore CPUs.
+In this configuration, the GenesysII is configured with a 32-bit version of the CVA6 RISC-V CPU.
+The SoC is configured with a memory controller interfacing with the Genesys' DRAM, PLIC and CLINT
+interrupt controllers, a UART device interfacing with the Genesys' USB UART, a RISC-V compatible
+debug module that interfaces with the Genesys' FTDI (USB JTAG) chip, a Xilinx SPI interface
+interfacing with the Genesys' SD card slot and a Xilinx GPIO interfacing with the Genesys' LEDs
+and switches.
+The complete hardware sources (see first reference) in conjunction with
+instructions for compiling and loading the configuration onto the GenesysII are available.
+
+.. figure:: genesysII.webp
+   :width: 800px
+   :align: center
+   :alt: Digilent GenesysII Board
+
+   Digilent GenesysII (Credit: Digilent)
+
+See the following references for more information:
+
+- `CVA6 documentation`_
+- `GenesysII Reference Manual`_
+- `GenesysII Schematic`_
+
+Hardware
+********
+
+- CVA6 CPU with RV32imac instruction sets with PLIC, CLINT interrupt controllers.
+- 1 GB DDR3 DRAM
+- 10/100/1000 Ethernet with copper interface, lowRISC Ethernet MAC
+- ns16550a-compatible USB UART, 115200 baud
+- RISCV debug module, connected via on-board FTDI (USB JTAG)
+- Xilinx SPI controller, connected to microSD slot
+- Xilinx GPIO, connected to 7 switches and LEDs
+
+Supported Features
+==================
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| INTERRUPT | on-chip    | RISC-V PLIC, CLIC (CLINT in CVA6)   |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | uart                                |
++-----------+------------+-------------------------------------+
+| JTAG      | on-chip    | openocd runner for west             |
++-----------+------------+-------------------------------------+
+
+
+Programming and Debugging
+*************************
+
+Loading the FPGA configuration
+==============================
+
+You need to build a bitstream with Xilinx Vivado and load it into the FPGA
+before you can load zephyr onto the board.
+Please refer to the CVA6 documentation for the required steps.
+This configuration is compatible with the following build targets:
+cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga.
+
+Flashing
+========
+west flash is supported via the openocd runner.
+
+Debugging
+=========
+west debug, attach and debugserver commands are supported via the openocd runner.
+
+
+References
+**********
+
+.. _CVA6 documentation:
+   https://github.com/openhwgroup/cva6
+
+.. _GenesysII Reference Manual:
+   https://digilent.com/reference/programmable-logic/genesys-2/reference-manual
+
+.. _GenesysII Schematic:
+   https://digilent.com/reference/_media/reference/programmable-logic/genesys-2/genesys-2_sch.pdf

boards/openhwgroup/cv32a6_genesysII/support/ariane.cfg

@@ -0,0 +1,49 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Based on the ariane.cfg from the cva6 project:
+# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg
+adapter_khz     1000
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+# Channel 1 is taken by Xilinx JTAG
+ftdi_channel 0
+
+# links:
+# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
+#
+# Bit  MPSSE     FT2232    JTAG    Type   Description
+# Bit0 TCK       ADBUS0    TCK     Out    Clock Signal Output
+# Bit1 TDI       ADBUS1    TDI     Out    Serial Data Out
+# Bit2 TDO       ADBUS2    TDO     In     Serial Data In
+# Bit3 TMS       ADBUS3    TMS     Out    Select Signal Out
+# Bit4 GPIOL0    ADBUS4    nTRST   In/Out General Purpose I/O
+# this corresponds to the following in/out layout, with TMS initially set to 1
+ftdi_layout_init 0x0018 0x001b
+# we only have to specify nTRST, the others are assigned correctly by default
+ftdi_layout_signal nTRST -ndata 0x0010
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba off
+
+# Try enabling address translation (only works for newer versions)
+if { [catch {riscv set_enable_virtual on} ] } {
+    echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
+
+init
+halt
+echo "Ready for Remote Connections"

boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV64A6_GENESYSII
+	select SOC_CV64A6_IMAFDC
+	select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF

boards/openhwgroup/cv64a6_genesysII/board.cmake

@@ -0,0 +1,8 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
+board_runner_args(openocd "--use-elf")
+board_runner_args(openocd "--verify")
+board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/openhwgroup/cv64a6_genesysII/board.yml

@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv64a6_genesysII
+  vendor: openhwgroup
+  socs:
+    - name: cv64a6

boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <openhwgroup/cv64a6.dtsi>
+
+/ {
+	model = "Openhardwaregroup CV64A6 on Genesys II";
+	compatible = "ariane,cv64a6_genesysII";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &memory0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <1 4>;
+};
+
+&spi0 {
+	status = "okay";
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <2 2>;
+};
+
+&clint{
+	status = "okay";
+};
+
+&dma0 {
+	status = "disabled";
+};
+
+
+&mdio0{
+	status = "disabled";
+};
+
+&eth0 {
+	status = "disabled";
+};
+
+&eth {
+	status = "okay";
+};
+
+&xlnx_gpio {
+	status = "okay";
+};

boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig

@@ -0,0 +1,40 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+CONFIG_CONSOLE_HANDLER=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000
+CONFIG_FPU=y
+CONFIG_POWEROFF=y
+
+# RNG
+CONFIG_TIMER_RANDOM_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+
+# IRQs
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+# 1 PLIC
+CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
+CONFIG_PLIC=y
+CONFIG_3RD_LEVEL_INTERRUPTS=n
+
+# no networking support on this board
+
+# logging
+CONFIG_LOG=y
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_THREAD_NAME=y
+
+# increased stack sizes
+CONFIG_ISR_STACK_SIZE=524288
+CONFIG_MAIN_STACK_SIZE=524288
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288
+CONFIG_IDLE_STACK_SIZE=524288