zephyrproject-rtos · nisarumar · Jul 6, 2023 · Jul 6, 2023 · Jul 6, 2023 · Jul 6, 2023
diff --git a/arch/x86/core/ia32/intstub.S b/arch/x86/core/ia32/intstub.S
@@ -13,6 +13,8 @@
  * exception) stubs are implemented in this module.  The stubs are invoked when
  * entering and exiting a C interrupt handler.
  */
+#define DT_DRV_COMPAT intel_loapic
+#define LOAPIC_BASE_ADDRESS DT_REG_ADDR(DT_DRV_INST(0))
 
 #include <zephyr/arch/x86/ia32/asm.h>
 #include <offsets_short.h>
@@ -197,10 +199,10 @@ alreadyOnIntStack:
 	wrmsr
 #else /* xAPIC */
 #ifdef DEVICE_MMIO_IS_IN_RAM
-	movl	z_loapic_regs, %edx
+	movl	Z_TOPLEVEL_RAM_NAME(loapic_regs), %edx
 	movl	%eax, LOAPIC_EOI(%edx)
 #else
-	movl	%eax, (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
+	movl	%eax, (LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
 #endif /* DEVICE_MMIO_IS_IN_RAM */
 #endif /* CONFIG_X2APIC */
 

diff --git a/arch/x86/core/intel64/locore.S b/arch/x86/core/intel64/locore.S
@@ -2,6 +2,8 @@
  * Copyright (c) 2019 Intel Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
+#define DT_DRV_COMPAT intel_loapic
+#define LOAPIC_BASE_ADDRESS DT_REG_ADDR(DT_DRV_INST(0))
 
 #include <zephyr/toolchain.h>
 #include <zephyr/arch/x86/multiboot.h>
@@ -142,7 +144,7 @@ x86_ap_start:
 	 * so we can locate our x86_cpuboot[] bundle. Put it in EBP.
 	 */
 
-	movl CONFIG_LOAPIC_BASE_ADDRESS+LOAPIC_ID, %eax
+	movl LOAPIC_BASE_ADDRESS+LOAPIC_ID, %eax
 	shrl $24, %eax
 	andl $0x0F, %eax		/* local APIC ID -> EAX */
 

@@ -9,12 +9,6 @@ menuconfig LOAPIC
 
 if LOAPIC
 
-config LOAPIC_BASE_ADDRESS
-	hex "Local APIC Base Address"
-	default 0xFEE00000
-	help
-	  This option specifies the base address of the Local APIC device.
-
 config X2APIC
 	bool "Access local APIC in x2APIC mode"
 	help

@@ -3,6 +3,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+
+#define DT_DRV_COMPAT intel_loapic
+
 /*
  * driver for x86 CPU local APIC (as an interrupt controller)
  */
@@ -59,18 +62,16 @@
 #define LOAPIC_SPURIOUS_VECTOR_ID CONFIG_LOAPIC_SPURIOUS_VECTOR_ID
 #endif
 
-#define LOPIC_SSPND_BITS_PER_IRQ  1  /* Just the one for enable disable*/
-#define LOPIC_SUSPEND_BITS_REQD (ROUND_UP((LOAPIC_IRQ_COUNT * LOPIC_SSPND_BITS_PER_IRQ), 32))
+#define LOAPIC_SSPND_BITS_PER_IRQ  1  /* Just the one for enable disable*/
+#define LOAPIC_SUSPEND_BITS_REQD (ROUND_UP((LOAPIC_IRQ_COUNT * LOAPIC_SSPND_BITS_PER_IRQ), 32))
 #ifdef CONFIG_PM_DEVICE
 #include <zephyr/pm/device.h>
 __pinned_bss
-uint32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
+uint32_t loapic_suspend_buf[LOAPIC_SUSPEND_BITS_REQD / 32] = {0};
 #endif
 
-#ifdef DEVICE_MMIO_IS_IN_RAM
-__pinned_bss
-mm_reg_t z_loapic_regs;
-#endif
+DEVICE_MMIO_TOPLEVEL(loapic_regs, DT_DRV_INST(0));
+#define LOAPIC_REG DEVICE_MMIO_TOPLEVEL_GET(loapic_regs)
 
 __pinned_func
 void send_eoi(void)
@@ -87,11 +88,8 @@ __pinned_func
 void z_loapic_enable(unsigned char cpu_number)
 {
 	int32_t loApicMaxLvt; /* local APIC Max LVT */
+    DEVICE_MMIO_TOPLEVEL_MAP(loapic_regs, K_MEM_CACHE_NONE);
 
-#ifdef DEVICE_MMIO_IS_IN_RAM
-	device_map(&z_loapic_regs, CONFIG_LOAPIC_BASE_ADDRESS, 0x1000,
-		   K_MEM_CACHE_NONE);
-#endif /* DEVICE_MMIO_IS_IN_RAM */
 #ifndef CONFIG_X2APIC
 	/*
 	 * in xAPIC and flat model, bits 24-31 in LDR (Logical APIC ID) are
@@ -340,7 +338,7 @@ static int loapic_suspend(const struct device *port)
 
 	ARG_UNUSED(port);
 
-	(void)memset(loapic_suspend_buf, 0, (LOPIC_SUSPEND_BITS_REQD >> 3));
+	(void)memset(loapic_suspend_buf, 0, (LOAPIC_SUSPEND_BITS_REQD >> 3));
 
 	for (loapic_irq = 0; loapic_irq < LOAPIC_IRQ_COUNT; loapic_irq++) {
 

diff --git a/dts/bindings/interrupt-controller/intel,loapic.yaml b/dts/bindings/interrupt-controller/intel,loapic.yaml
@@ -0,0 +1,22 @@
+description: Local Advanced Programmable Interrupt Controller (APIC)
+
+compatible: "intel,loapic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  num-irqs:
+    type: int
+    required: true
+    description: architecturally defined maximum number of LVTs
+
+  "#interrupt-cells":
+    const: 3
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
diff --git a/dts/x86/intel/apollo_lake.dtsi b/dts/x86/intel/apollo_lake.dtsi
@@ -35,6 +35,14 @@
 		#interrupt-cells = <3>;
 	};
 
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		num-irqs = <6>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
 	pcie0: pcie0 {
 		#address-cells = <1>;
 		#size-cells = <1>;

diff --git a/dts/x86/intel/atom.dtsi b/dts/x86/intel/atom.dtsi
@@ -32,6 +32,14 @@
 		#interrupt-cells = <3>;
 	};
 
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		num-irqs = <6>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;

diff --git a/dts/x86/intel/elkhart_lake.dtsi b/dts/x86/intel/elkhart_lake.dtsi
@@ -40,6 +40,14 @@
 		#interrupt-cells = <3>;
 	};
 
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		num-irqs = <6>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
 	pcie0: pcie0 {
 		#address-cells = <1>;
 		#size-cells = <1>;

diff --git a/dts/x86/intel/ia32.dtsi b/dts/x86/intel/ia32.dtsi
@@ -28,6 +28,14 @@
 		#interrupt-cells = <3>;
 	};
 
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		num-irqs = <6>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
 	dram0: memory@0 {
 		device_type = "memory";
 		reg = <DT_DRAM_BASE DT_DRAM_SIZE>;

diff --git a/dts/x86/intel/lakemont.dtsi b/dts/x86/intel/lakemont.dtsi
@@ -28,6 +28,14 @@
 		#interrupt-cells = <3>;
 	};
 
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		num-irqs = <6>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
 	/*
 	 * Platforms with Lakemont SoC can have different hardware
 	 * configurations. So RAM and peripherals need to be

diff --git a/dts/x86/intel/raptor_lake.dtsi b/dts/x86/intel/raptor_lake.dtsi
@@ -35,6 +35,14 @@
 		#interrupt-cells = <3>;
 	};
 
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		num-irqs = <6>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
 	pcie0: pcie0 {
 		#address-cells = <1>;
 		#size-cells = <1>;

diff --git a/include/zephyr/drivers/interrupt_controller/loapic.h b/include/zephyr/drivers/interrupt_controller/loapic.h
@@ -71,11 +71,8 @@ static inline uint64_t x86_read_x2apic(unsigned int reg)
 	reg >>= 4;
 	return z_x86_msr_read(X86_X2APIC_BASE_MSR + reg);
 }
-
 /* Defined in intc_loapic.c */
-#ifdef DEVICE_MMIO_IS_IN_RAM
-extern mm_reg_t z_loapic_regs;
-#endif
+DEVICE_MMIO_TOPLEVEL_DECLARE(loapic_regs);
 
 /**
  * @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
@@ -85,11 +82,7 @@ extern mm_reg_t z_loapic_regs;
 static inline uint32_t x86_read_xapic(unsigned int reg)
 {
 	mm_reg_t base;
-#ifdef DEVICE_MMIO_IS_IN_RAM
-	base = z_loapic_regs;
-#else
-	base = CONFIG_LOAPIC_BASE_ADDRESS;
-#endif
+	base = DEVICE_MMIO_TOPLEVEL_GET(loapic_regs);
 	return sys_read32(base + reg);
 }
 
@@ -133,11 +126,7 @@ static inline void x86_write_x2apic(unsigned int reg, uint64_t val)
 static inline void x86_write_xapic(unsigned int reg, uint32_t val)
 {
 	mm_reg_t base;
-#ifdef DEVICE_MMIO_IS_IN_RAM
-	base = z_loapic_regs;
-#else
-	base = CONFIG_LOAPIC_BASE_ADDRESS;
-#endif
+	base = DEVICE_MMIO_TOPLEVEL_GET(loapic_regs);
 	sys_write32(val, base + reg);
 }