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drivers: spi: spi_nrfx_spim: Add CPOL handling on SCK pin #61294

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merged 2 commits into from
Aug 9, 2023

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Pin state after SPIM deinitialization is based on pinctrl configuration. On the other hand, CPOL is set during runtime. With the introduction of the power-optimized SPIM driver, it disables the peripheral instance once the transfer is completed. As a result, the GPIO takes control over the SCK pin and drives it based on pinctrl configuration which causes an invalid SCK state when the transaction is configured with CPOL (Clock Polarity).

To address this issue, a patch was introduced to the SPIM driver. Now, when a SPIM instance is configured with CPOL, the driver is setting in the runtime the correct state of the SCK pin.

The PR addresses concerns in the comment #61280 (comment) placed in PR with another solution to CPOL handling on SCK pin.

drivers/spi/spi_nrfx_spim.c Outdated Show resolved Hide resolved
@awojasinski awojasinski force-pushed the spi-cpol-sck branch 2 times, most recently from 0db7ed3 to c371443 Compare August 8, 2023 18:22
anangl
anangl previously approved these changes Aug 9, 2023
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Could you also provide the same correction in spi_nrfx_spi.c?

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anangl commented Aug 9, 2023

I guess #61280 can be closed.

Adam Wojasinski added 2 commits August 9, 2023 17:13
Pin state after SPIM deinitialization is based on pinctrl configuration.
On the other hand, CPOL is set during runtime. With the introduction
of the power-optimized SPIM driver, it disables the peripheral instance
once the transfer is completed.
As a result, the GPIO takes control over the SCK pin and drives it
based on pinctrl configuration which causes an invalid SCK state
when the transaction is configured with CPOL (Clock Polarity).

To address this issue, a patch was introduced to the SPIM driver.
Now, when a SPIM instance is configured with CPOL,
the driver is setting in the runtime the correct state of the SCK pin.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Pin state after SPI deinitialization is based on pinctrl configuration.
On the other hand, CPOL is set during runtime. When the SPI instance
is disabled GPIO takes control over SCK and drives it to state set
by pinctrl driver. This might causes an invalid SCK state
when the transaction is configured with CPOL (Clock Polarity).

To address this issue, a patch was introduced to the SPI driver.
Now, when a SPI instance is configured with CPOL,
the driver is setting in the runtime the correct state of the SCK pin.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
@fabiobaltieri fabiobaltieri merged commit 9de69aa into zephyrproject-rtos:main Aug 9, 2023
15 checks passed
@awojasinski awojasinski deleted the spi-cpol-sck branch January 9, 2024 16:36
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5 participants