soc: intel_adsp: replace icache ISR workaround with custom idle solution

arch/xtensa/include/xtensa_asm2_s.h

@@ -609,11 +609,6 @@ _Level\LVL\()Vector:
 	s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
 	s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
 
-#ifdef CONFIG_ADSP_IDLE_CLOCK_GATING
-	/* Needed when waking from low-power waiti state */
-	isync
-#endif
-
 	/* Level "1" is the exception handler, which uses a different
 	 * calling convention.  No special register holds the
 	 * interrupted PS, instead we just assume that the CPU has

soc/intel/intel_adsp/ace/Kconfig

@@ -8,6 +8,7 @@ config SOC_SERIES_INTEL_ADSP_ACE
 	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
 	select ARCH_HAS_COHERENCE
 	select SCHED_IPI_SUPPORTED
+	select ARCH_CPU_IDLE_CUSTOM
 	select DW_ICTL_ACE
 	select SOC_HAS_RUNTIME_NUM_CPUS
 	select HAS_PM

soc/intel/intel_adsp/ace/power.c

@@ -437,3 +437,25 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 #endif /* CONFIG_PM */
+
+#ifdef CONFIG_ARCH_CPU_IDLE_CUSTOM
+
+__no_optimization
+void arch_cpu_idle(void)
+{
+	uint32_t cpu = arch_proc_id();
+
+	sys_trace_idle();
+
+	/*
+	 * unlock and invalidate icache if clock gating is allowed
+	 */
+	if (!(DSPCS.bootctl[cpu].bctl & DSPBR_BCTL_WAITIPCG)) {
+		xthal_icache_all_unlock();
+		xthal_icache_all_invalidate();
+	}
+
+	__asm__ volatile ("waiti 0");
+}
+
+#endif /* CONFIG_ARCH_CPU_IDLE_CUSTOM */