boards: openhwgroup: add CV64A6 Testbench #77789
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nordicjm
requested changes
Sep 11, 2024
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| # SPDX-License-Identifier: Apache-2.0 | |||
| CONFIG_3RD_LEVEL_INTERRUPT_BITS=0 | ||
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| # debug |
Adds support for the CVA6 CPU in the hardware simulation / testbench environment. Especially, configurations are added that allow the application to indicate success or error to the testbench. The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem (which is currently without a driver in zephyr). Two sample applications are provided, demonstrating how to indicate success or failure to the testbench. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
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Merged into #77732 |
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Adds support for the CVA6 CPU in the hardware simulation / testbench environment. Especially, configurations are added that allow the application to indicate success or error to the testbench. The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem (which is currently without a driver in zephyr).
Two sample applications are provided, demonstrating how to indicate success or failure to the testbench.