Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

boards: openhwgroup: add CV64A6 Testbench #77789

Closed
wants to merge 1 commit into from
Closed

boards: openhwgroup: add CV64A6 Testbench #77789

wants to merge 1 commit into from

Commits on Oct 2, 2024

  1. boards: openhwgroup: add CV64A6 Testbench 

    Adds support for the CVA6 CPU in the hardware simulation / testbench
environment. Especially, configurations are added that allow the
application to indicate success or error to the testbench.
The SoC currently contains the CVA6 CPU in 64-bit configuration with the
SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for
booting from SD, a boot ROM, and I2C controller for on-board audio, a
GPIO and the lowRISC ethernet subsystem (which is currently without a
driver in zephyr).
Two sample applications are provided, demonstrating how to indicate
success or failure to the testbench.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
    @WorldofJARcraft
    WorldofJARcraft committed Oct 2, 2024
    Configuration menu
    Copy the full SHA
    7565392 View commit details
    Browse the repository at this point in the history