boards: openhwgroup: add CV64A6 on GenesysII board #77792
Closed
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
1 task
Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
WorldofJARcraft
force-pushed
the
cv64a6-genesysii-upstream
branch
from
70211f4
to
68fa8f0
Compare
|
Merged into #77732 |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6).
The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem.