Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[WIP] stm32 mspi drivers for the MSPI flash and controller #78186

Draft
wants to merge 15 commits into
base: main
Choose a base branch
from

Conversation

FRASTM
Copy link
Collaborator

@FRASTM FRASTM commented Sep 9, 2024

this PR is introducing the MSPI driver device a controller for the stm32 mcus : stm32H5 serie

  • MSPI device = nor flash node drivers/flash/flash_mspi_nor_mx typically the mx25lm51245 mounted on the disco kit
    ---> compat is mspi_nor_mx25
  • MSPI controller : drivers/mspi/mspi_stm 32 typically the octospi peripherals of the stm32 devices.
    ---> compat is st,stm32-mspi-controller

Build an run the samples/drivers/mspi/mspi_flash/ on stm32h573i_dk disco kit​

  • only SPI / STR mode : configure/
  • SPI / STR mode : read (in async. IT ) ​
  • SPI / STR mode : erase/write (in async. IT ) wait for mem ready (typ. SPI_NOR_WEL_MATCH/SPI_NOR_WEL_MASK)
  • OPI/QUAD and DTR mode : configure/erase/read/write (octal commands)​
  • read/erase/write with DMA
  • XIP configuration (stm32 memorymap mode)​
  • Support more platforms (and NOR flash devices)​
  • Support psRAM device

@FRASTM FRASTM changed the title stm32 mspi drivers for the MSPI flash and controller [WIP] stm32 mspi drivers for the MSPI flash and controller Sep 10, 2024
Add the mspi-device and mspi-flash controller bindings
for the stm32 devices.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace the xpsi by the mspi node in the DTS
of the stm32h5 serie

Signed-off-by: Francois Ramu <francois.ramu@st.com>
@FRASTM FRASTM force-pushed the mspi_stm32 branch 4 times, most recently from 6dd0042 to c574a3d Compare September 12, 2024 16:21
@FRASTM
Copy link
Collaborator Author

FRASTM commented Sep 12, 2024

reading external NOR at offset 0 in spi/str mode :

Perform test read on single sector
 command Instruction = 0x13
Data read at is 
Read at 00000000 read 08
Read at 00000001 read b5
Read at 00000002 read 06
Read at 00000003 read 4a                                                        
Read at 00000004 read 06                                                        
Read at 00000005 read 49                                                        
Read at 00000006 read 07                                                        
Read at 00000007 read 48                                                        
Read at 00000008 read 00                                                        
Read at 00000009 read f0                                                        
Read at 0000000a read 12                                                        
Read at 0000000b read f8                                                        
Read at 0000000c read bd                                                        
Read at 0000000d read e8                                                        
Read at 0000000e read 08                                                        
Read at 0000000f read 40  
Perform test on single sector                                                                                
Test 1: Flash erase at 0xff000                                                                               
Flash erase succeeded!                                                                                       
                                                                                                             
Test 2: Flash write at 0xff000                                                                               
Attempting to write 4 bytes                                                                                  
                                                                                                             
Test 3: Flash read at 0xff000                                                                                
Data read matches data written. Good!!                                                                       
                                                                                                             
Perform test on multiple consecutive sectors                                                                 
Test 1: Flash erase from 0xff000                                                                             
Flash erase succeeded!                                                                                       
                                                                                                             
Test 2: Flash write from 0xff000                                                                             
Attempting to write 4 bytes at offset 0xff000                                                                
Attempting to read 4 bytes at offset 0xff000                                                                 
Data read matches data written. Good!!                                                                       
Attempting to write 4 bytes at offset 0x100000                                                               
Attempting to read 4 bytes at offset 0x100000                                                                
Data read matches data written. Good!!                                                                       
==========================        

@FRASTM FRASTM force-pushed the mspi_stm32 branch 3 times, most recently from f06b0df to 533c0a2 Compare September 13, 2024 15:20
Declare the mspi node of the stm32h573i_dk in place
of the xspi.
New properties are declared according to the
mspi-controller.yaml.
Only SPi/STR supported yet. XIP not supported yet.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable the stm32 MSPI controller based on the xspi peripheral

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable the  MSPI NOR multi-SPI flash device accessed through
a mspi controller

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the functions to verfify device and configure
the mspi controller device.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Make the read and write access to the mspi NOR device
in sync/async PIO and DMA bus mode.
Including the dummyCycles

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Propose read an write access in sync/ascync on PIO/DMA
to the flash device.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
For stm32 mcus, this commit adds a reset, jedec and
configuration commands to be sent to the device
through the mspi controller.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds a reset and jedec
commands and a memory configuration io_mode/data_rate
sent to the NOR flash device through the controller.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add another mode for selecting read/write the status reg
of a device

Signed-off-by: Francois Ramu <francois.ramu@st.com>
@FRASTM FRASTM force-pushed the mspi_stm32 branch 7 times, most recently from 0ae83b8 to d44c5c4 Compare September 23, 2024 13:23
@FRASTM FRASTM force-pushed the mspi_stm32 branch 2 times, most recently from 47489b7 to 76f3f37 Compare September 23, 2024 15:06
@FRASTM FRASTM force-pushed the mspi_stm32 branch 6 times, most recently from a18d64e to a63ea6e Compare September 27, 2024 09:38
Declare the stm32h573i_dk node to be MSPI compatible when running
the samples/drivers/jesd216 or samples/drivers/mspi/
Only SPI/STR mode.
No DMA in this version.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a function to poll the NOR flash status register with a MSPI_REG
set as direction and bit mask/value se to the packet structure
This info is going to the MSPI driver through mspi_transceive function

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Get the bit mask/value structure when polling the device
status register bits and send
the corresponding HAL_XSPI_AutoPolling function. This function
is blocking until the callback matches the expected bits.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant