autowrap and network construction features

[sgherbst]

This PR adds a couple of new features:

1. autowrap feature for SbDut that automatically generates Verilog wrapper code to instantiate a DUT and connect it to switchboard modules. This can eliminate the need to create a testbench.sv file in some cases.
2. SbNetwork class allowing for the dynamic construction of networks of simulations. See examples/network for an example and documentation.
3. Rate limiting: specify --max-rate X when running switchboard simulations to limit the speed of simulations and switchboard packet transmission to X Hz in wall time. This comes in handy in several cases: (1) prevents generating giant VCD files, (2) makes it easier to saturate links since the driver doesn't need to be as fast, and (3) makes it easier to achieve good sharing of processor cores when running many simulations in parallel.
   • Note: --max-rate X assumes cmdline=True was set for SbDut; if not, specify max_rate=X argument in the SbDut constructor. cmdline=True is a relatively new feature - it presents a standard command-line interface for setting tool, fast, trace, etc.

These new features are big enough that I think it's worth bumping the version number of switchboard to 0.2.0. This new version should be fully backwards-compatible with 0.1.0.

Future updates planned for 0.2.X include:

1. Option to have SbNetwork compile into a single-netlist Verilog simulation for best accuracy.
2. Option to use SbNetwork as a component in an SbNetwork. This, combined with (1), would allow for networks to be simulated by connecting together RTL simulations of sub-networks.
3. Option for SbNetwork.connect() to connect over TCP to remote machines.

[azaidy]

LGTM!

[azaidy]

Probably a typo. Should be axil = dut.intfs['s_axil']

[sgherbst]

Thanks, good catch - fixed