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autowrap and network construction features #212
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8cde8dd
work in progress
sgherbst 2ac6a13
automatically set up interfaces
sgherbst 4bcbdc3
get autowrap working for axi and axil
sgherbst 763f341
further simplification of examples using autowrap
sgherbst 875430d
new mechanism for accessing interfaces
sgherbst b6d7252
work in progress
sgherbst 60f7c3c
umi_fifo network example works
sgherbst f388f89
fix bug in example
sgherbst be40b9d
update network example to use two rtl modules
sgherbst 44c3ac9
automatically clean up queues created during a network simulation
sgherbst 613366d
clean up diff
sgherbst 11503b4
more interesting network example
sgherbst 7ebe2ac
add network example to regression testing
sgherbst 85eab26
remove network simulation from tests as an experiment
sgherbst be9b413
update documentation
sgherbst a40c8c1
max_rate and start_delay features for verilator and pybind
sgherbst d2875b2
fix bug in axi-lite max-rate implementation
sgherbst bc8698b
try adding verilator network test
sgherbst ee25b1d
implement max_rate and start_delay for non-verilator simulators
sgherbst 8ffb423
fix bug in max_rate_tick
sgherbst 4d65701
adjust max_rate behavior (work in progress)
sgherbst 63ac1df
try disabling minimal test as an experiment
sgherbst 5b7e567
run only the network test
sgherbst 33e9e80
fix umi version for regression test
sgherbst c63e23e
fix lint
sgherbst 2876815
fix mismatches in code vs documentation for examples
sgherbst ad87041
update documentation
sgherbst 77eeaf7
Merge branch 'main' into sgh/autowrap
sgherbst 5d93f65
Merge branch 'main' into sgh/autowrap
sgherbst c4f7f0d
fix typo
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Original file line number | Diff line number | Diff line change |
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// Copyright (c) 2024 Zero ASIC Corporation | ||
// This code is licensed under Apache License 2.0 (see LICENSE for details) | ||
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`default_nettype none | ||
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`include "switchboard.vh" | ||
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module sb_loopback #( | ||
parameter DW=256, | ||
parameter [7:0] INCREMENT=1 | ||
) ( | ||
input clk, | ||
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`SB_INPUT(in, DW), | ||
`SB_OUTPUT(out, DW) | ||
); | ||
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// loopback with increment | ||
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genvar i; | ||
generate | ||
for (i=0; i<(DW/8); i=i+1) begin | ||
assign out_data[(i*8) +: 8] = in_data[(i*8) +: 8] + INCREMENT; | ||
end | ||
endgenerate | ||
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assign out_dest = in_dest; | ||
assign out_last = in_last; | ||
assign out_valid = in_valid; | ||
assign in_ready = out_ready; | ||
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endmodule | ||
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`default_nettype wire |
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Probably a typo. Should be axil = dut.intfs['s_axil']
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Thanks, good catch - fixed