Added STIDC and UTIDC registers #247
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The current spec has UTID as a view of STID (and no MTID at all), do we want to match that instead? |
That's being changed, it was a bad idea to not have a separate ID register for S-mode's own use |
| @@ -165,6 +181,10 @@ void HELPER(cspecialrw)(CPUArchState *env, uint32_t cd, uint32_t cs, | |||
| _host_return_address); | |||
| } | |||
| bool can_access_sysregs = cheri_have_access_sysregs(env); | |||
| bool is_write = (cs != 0); | |||
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Introducing a variable for this when there are multiple existing, untouched uses of cs != 0 isn't particularly clean
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@jrtc27 The same would then apply to bool can_access_sysregs. I attempted to use the style of the code around, but I am more than happy to directly use cs != 0. I did not spot a variable that would give me the same semantics, but I might have missed it.
| ASR_W_Flag = 2, | ||
| U_Always = (PRV_U + 1) << 2, | ||
| U_ASR_W = U_Always | ASR_W_Flag, | ||
| U_ASR = U_ASR_W | ASR_Flag, |
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U_ASR is ASR + ASR_W, which is a bit odd (i.e. you're inconsistent between the flag and the aliases what the unsuffixed version means)
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Also, U_Always | ASR_Flag and U_Always | ASR_Flag | ASR_W_Flag behave the same, which is a bit confusing too IMO
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@jrtc27 Would ASR_RW = ASR_R | ASR_W be something you are happy with? Then all SCRs other than xTIDC need to have ASR_RW.
This PR adds the SCRs for supervisor and user thread ID capability registers, which are used in compartmentalisation.