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Added STIDC and UTIDC registers #247

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Added STIDC and UTIDC registers #247

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02032d2
Added STIDC and UTIDC registers
francislaus Apr 18, 2024
1fd9a10
Changed numbers for STIDC and UTIDC
francislaus Apr 19, 2024
986f0a1
Added MTIDC registers and enforced ASR only on writes for xTIDC regis…
francislaus May 8, 2024
d8b4544
Fixed error in is_write logic
francislaus May 8, 2024
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2 changes: 2 additions & 0 deletions target/riscv/cheri-archspecific-early.h
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Original file line number Diff line number Diff line change
Expand Up @@ -84,11 +84,13 @@ enum CheriSCR {
CheriSCR_UTDC = 5,
CheriSCR_UScratchC = 6,
CheriSCR_UEPCC = 7,
CheriSCR_UTIDC = 8,
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CheriSCR_STCC = 12,
CheriSCR_STDC = 13,
CheriSCR_SScratchC = 14,
CheriSCR_SEPCC = 15,
CheriSCR_STIDC = 16,

CheriSCR_MTCC = 28,
CheriSCR_MTDC = 29,
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2 changes: 2 additions & 0 deletions target/riscv/cpu.c
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Expand Up @@ -743,11 +743,13 @@ static void riscv_cpu_reset(DeviceState *dev)
null_capability(&env->UTDC);
null_capability(&env->UScratchC);
set_max_perms_capability(&env->UEPCC, 0);
null_capability(&env->UTIDC);
// Supervisor mode trap handling
set_max_perms_capability(&env->STCC, 0);
null_capability(&env->STDC);
null_capability(&env->SScratchC);
set_max_perms_capability(&env->SEPCC, 0);
null_capability(&env->STIDC);
// Machine mode trap handling
set_max_perms_capability(&env->MTCC, 0);
null_capability(&env->MTDC);
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2 changes: 2 additions & 0 deletions target/riscv/cpu.h
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Expand Up @@ -204,13 +204,15 @@ struct CPURISCVState {
cap_register_t UTDC; // SCR 5 User trap data cap. (UTDC)
cap_register_t UScratchC; // SCR 6 User scratch cap. (UScratchC)
cap_register_t UEPCC; // SCR 7 User exception PC cap. (UEPCC)
cap_register_t UTIDC; // SCR 8 User thread identifier cap. (UTIDC)
#endif

#ifdef TARGET_CHERI
cap_register_t STCC; // SCR 12 Supervisor trap code cap. (STCC)
cap_register_t STDC; // SCR 13 Supervisor trap data cap. (STDC)
cap_register_t SScratchC; // SCR 14 Supervisor scratch cap. (SScratchC)
cap_register_t SEPCC; // SCR 15 Supervisor exception PC cap. (SEPCC)
cap_register_t STIDC; // SCR 16 Supervisor thread identifier cap. (STIDC)
#else
target_ulong stvec;
target_ulong sepc;
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4 changes: 4 additions & 0 deletions target/riscv/op_helper_cheri.c
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Expand Up @@ -89,6 +89,7 @@ struct SCRInfo {
.access = U_ASR,
.name = "UScratchC"},
[CheriSCR_UEPCC] = {.r = true, .w = true, .access = U_ASR, .name = "UEPCC"},
[CheriSCR_UTIDC] = {.r = true, .w = false, .access = U_Always, .name = "UTIDC"},

[CheriSCR_STCC] = {.r = true, .w = true, .access = S_ASR, .name = "STCC"},
[CheriSCR_STDC] = {.r = true, .w = true, .access = S_ASR, .name = "STDC"},
Expand All @@ -97,6 +98,7 @@ struct SCRInfo {
.access = S_ASR,
.name = "SScratchC"},
[CheriSCR_SEPCC] = {.r = true, .w = true, .access = S_ASR, .name = "SEPCC"},
[CheriSCR_STIDC] = {.r = true, .w = true, .access = S_ASR, .name = "STIDC"},

[CheriSCR_MTCC] = {.r = true, .w = true, .access = M_ASR, .name = "MTCC"},
[CheriSCR_MTDC] = {.r = true, .w = true, .access = M_ASR, .name = "MTDC"},
Expand All @@ -123,11 +125,13 @@ static inline cap_register_t *get_scr(CPUArchState *env, uint32_t index)
case CheriSCR_UTDC: return &env->UTDC;
case CheriSCR_UScratchC: return &env->UScratchC;
case CheriSCR_UEPCC: return &env->UEPCC;
case CheriSCR_UTIDC: return &env->UTIDC;

case CheriSCR_STCC: return &env->STCC;
case CheriSCR_STDC: return &env->STDC;
case CheriSCR_SScratchC: return &env->SScratchC;
case CheriSCR_SEPCC: return &env->SEPCC;
case CheriSCR_STIDC: return &env->STIDC;

case CheriSCR_MTCC: return &env->MTCC;
case CheriSCR_MTDC: return &env->MTDC;
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