#28 MIXED_WIDTH doesn't need an extra bit anymore

SpinalHDL · Sep 23, 2024 · 13da151 · 13da151
1 parent 1b44b20
commit 13da151
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Showing 3 changed files with 4 additions and 3 deletions.
diff --git a/ext/NaxSoftware b/ext/NaxSoftware
diff --git a/src/main/scala/vexiiriscv/fetch/PcPlugin.scala b/src/main/scala/vexiiriscv/fetch/PcPlugin.scala
@@ -50,7 +50,8 @@ class PcPlugin(var resetVector : BigInt = 0x80000000l) extends FiberPlugin with
       val self = new Area {
         val id = Reg(Fetch.ID) init(0)
         val flow = newJumpInterface(-1, laneAgeWidth = 0, aggregationPriority = 0)
-        val increment, fault = RegInit(False)
+        val increment = RegInit(False)
+        val fault = RegInit(False) simPublic()
         val state = Reg(PC) init (resetVector) simPublic()
         val pc = state + U(WORD_BYTES).andMask(increment)
         flow.valid := True

diff --git a/src/main/scala/vexiiriscv/memory/MmuPlugin.scala b/src/main/scala/vexiiriscv/memory/MmuPlugin.scala
@@ -162,7 +162,7 @@ class MmuPlugin(var spec : MmuSpec,
 
     PHYSICAL_WIDTH.set(physicalWidth)
     VIRTUAL_WIDTH.set(spec.virtualWidth)
-    MIXED_WIDTH.set(VIRTUAL_WIDTH.get + (VIRTUAL_WIDTH < XLEN).toInt)
+    MIXED_WIDTH.set(VIRTUAL_WIDTH.get)
     PC_WIDTH.set(MIXED_WIDTH)
     TVAL_WIDTH.set(MIXED_WIDTH)
     assert(VIRTUAL_WIDTH.get == XLEN.get || XLEN.get > VIRTUAL_WIDTH.get && VIRTUAL_WIDTH.get > physicalWidth)