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add MacRxCheckSumChecker Scala CI #413: Commit ca10ab5 pushed by Dolu1990
October 24, 2024 13:03 3m 43s dev
dev
October 24, 2024 13:03 3m 43s
Fix fetch next line prefetcher Scala CI #412: Commit 4e3be31 pushed by Dolu1990
October 22, 2024 15:18 3m 26s dev
dev
October 22, 2024 15:18 3m 26s
Add support for cacheless FPU configurations Scala CI #411: Commit 2d24a50 pushed by Dolu1990
October 22, 2024 09:54 3m 46s dev
dev
October 22, 2024 09:54 3m 46s
Merge pull request #30 from SpinalHDL/mac Scala CI #410: Commit a6f1e8e pushed by Dolu1990
October 22, 2024 08:01 3m 28s dev
dev
October 22, 2024 08:01 3m 28s
Add litex gigabit ethernet support Scala CI #409: Pull request #30 opened by Dolu1990
October 22, 2024 08:01 3m 29s mac
mac
October 22, 2024 08:01 3m 29s
sync Scala CI #408: Commit 3a5da24 pushed by Dolu1990
October 22, 2024 07:37 3m 42s mac
mac
October 22, 2024 07:37 3m 42s
Add ElfMapper Scala CI #407: Commit 0119a6d pushed by Dolu1990
October 17, 2024 14:21 3m 28s mac
mac
October 17, 2024 14:21 3m 28s
rgmii works Scala CI #406: Commit 2760d80 pushed by Dolu1990
October 11, 2024 22:06 1m 6s mac
mac
October 11, 2024 22:06 1m 6s
sync SpinalHDL mac rx Scala CI #405: Commit d18c353 pushed by Dolu1990
October 9, 2024 13:37 58s mac
mac
October 9, 2024 13:37 58s
workaround RISC-V debug spec with no debug trigger Scala CI #404: Commit 1b81c19 pushed by Dolu1990
October 3, 2024 18:57 3m 23s dev
dev
October 3, 2024 18:57 3m 23s
sync Scala CI #403: Commit a44cd59 pushed by Dolu1990
October 3, 2024 12:53 3m 10s mac
mac
October 3, 2024 12:53 3m 10s
sync SpinalHDL Scala CI #402: Commit fa91d9e pushed by Dolu1990
October 2, 2024 12:57 3m 27s mac
mac
October 2, 2024 12:57 3m 27s
Litex soc mac wip Scala CI #401: Commit 5d8d79c pushed by Dolu1990
October 2, 2024 12:57 3m 24s mac
mac
October 2, 2024 12:57 3m 24s
#26 GenerateTilelink now patch mem.a.mask to be compliant Scala CI #400: Commit b9f015a pushed by Dolu1990
September 26, 2024 10:40 3m 21s dev
dev
September 26, 2024 10:40 3m 21s
Got FPU added to the automated regressions Scala CI #399: Commit ed1969f pushed by Dolu1990
September 25, 2024 17:18 3m 26s dev
dev
September 25, 2024 17:18 3m 26s
Fix FpuAddSharedPlugin packPort.cmd.at usage Scala CI #398: Commit 0e3bb7f pushed by Dolu1990
September 25, 2024 15:39 4m 2s dev
dev
September 25, 2024 15:39 4m 2s
#27 Allows debug triggers without having debug support. Allow debug t… Scala CI #397: Commit d46e9bf pushed by Dolu1990
September 24, 2024 13:12 3m 47s dev
dev
September 24, 2024 13:12 3m 47s
sync Scala CI #396: Commit 91cc127 pushed by Dolu1990
September 23, 2024 16:37 4m 5s dev
dev
September 23, 2024 16:37 4m 5s
#28 fix debug trigger Scala CI #395: Commit eec2859 pushed by Dolu1990
September 23, 2024 14:23 3m 42s dev
dev
September 23, 2024 14:23 3m 42s
#28 MIXED_WIDTH doesn't need an extra bit anymore Scala CI #394: Commit 13da151 pushed by Dolu1990
September 23, 2024 13:29 4m 0s dev
dev
September 23, 2024 13:29 4m 0s
fix #27 tselect is now always implemented Scala CI #393: Commit e2a1b1f pushed by Dolu1990
September 23, 2024 08:11 3m 39s dev
dev
September 23, 2024 08:11 3m 39s
Got marchid 46 Scala CI #392: Commit ffeaa79 pushed by Dolu1990
September 23, 2024 06:04 3m 29s dev
dev
September 23, 2024 06:04 3m 29s
#26 fix GenerateTilelink mem bus data width Scala CI #391: Commit 194adb4 pushed by Dolu1990
September 20, 2024 21:42 3m 18s dev
dev
September 20, 2024 21:42 3m 18s
#26 GenerateTilelink now report tilelink source ID Scala CI #390: Commit 2cd18f9 pushed by Dolu1990
September 20, 2024 20:12 3m 28s dev
dev
September 20, 2024 20:12 3m 28s
#26 add --tl-sink-width=Int Scala CI #389: Commit bd36a07 pushed by Dolu1990
September 20, 2024 16:23 3m 49s dev
dev
September 20, 2024 16:23 3m 49s