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SpinalHDL · Sep 23, 2024 · 91cc127 · 91cc127
1 parent be5c857
commit 91cc127
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Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -262,8 +262,8 @@ class ParamSimple(){
 
 
     privParam.withDebug = true
-//    privParam.debugTriggers = 4
-//    privParam.debugTriggersLsu = true
+    privParam.debugTriggers = 4
+    privParam.debugTriggersLsu = true
     embeddedJtagTap = true
 
 

diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala
@@ -462,6 +462,8 @@ object SocGen extends App{
 //  val from = cpu0.reflectBaseType("LsuL1Plugin_logic_c_pip_ctrl_2_up_onPreCtrl_HIT_DIRTY") //That big
 //  val to = cpu0.reflectBaseType("PrivilegedPlugin_logic_harts_0_debug_dcsr_stepLogic_stepped")
 
+//  val from = cpu0.reflectBaseType("early0_SrcPlugin_logic_addsub_combined_rs2Patched") //That big
+//  val to = cpu0.reflectBaseType("toplevel_execute_ctrl2_up_early0_SrcPlugin_SRC2_lane0")
 
 
 //  val drivers = mutable.LinkedHashSet[BaseType]()