#26 fix GenerateTilelink mem bus data width

SpinalHDL · Sep 20, 2024 · 194adb4 · 194adb4
1 parent 2cd18f9
commit 194adb4
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/vexiiriscv/Generate.scala b/src/main/scala/vexiiriscv/Generate.scala
@@ -65,7 +65,7 @@ object GenerateTilelink extends App {
       val mem = new SlaveBus(
         M2sSupport(
           transfers = M2sTransfers.all,
-          dataWidth = param.xlen,
+          dataWidth = param.memDataWidth,
           addressWidth = param.physicalWidth
         ),
         S2mParameters(