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@Dolu1990
Dolu1990 committed Jul 12, 2024
1 parent 6bb08c8 commit 1a92afb
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Showing 3 changed files with 35 additions and 3 deletions.
4 changes: 2 additions & 2 deletions src/main/scala/vexiiriscv/Param.scala
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Expand Up @@ -330,7 +330,7 @@ class ParamSimple(){
opt[Unit]("lsu-l1") action { (v, c) => lsuL1Enable = true }
opt[Int]("fetch-l1-sets") unbounded() action { (v, c) => fetchL1Sets = v }
opt[Int]("fetch-l1-ways") unbounded() action { (v, c) => fetchL1Ways = v }
opt[Int]("fetch-l1-mem-data-width-min") action { (v, c) => fetchMemDataWidthMin = v }
opt[Int]("fetch-l1-mem-data-width-min") unbounded() action { (v, c) => fetchMemDataWidthMin = v }
opt[Unit]("fetch-reduced-bank") action { (v, c) => fetchL1ReducedBank = true }
opt[Int]("lsu-l1-sets") unbounded() action { (v, c) => lsuL1Sets = v }
opt[Int]("lsu-l1-ways") unbounded() action { (v, c) => lsuL1Ways = v }
Expand All @@ -340,7 +340,7 @@ class ParamSimple(){
opt[Unit]("lsu-software-prefetch") action { (v, c) => lsuSoftwarePrefetch = true }
opt[Int]("lsu-l1-refill-count") action { (v, c) => lsuL1RefillCount = v }
opt[Int]("lsu-l1-writeback-count") action { (v, c) => lsuL1WritebackCount = v }
opt[Int]("lsu-l1-mem-data-width-min") action { (v, c) => lsuMemDataWidthMin = v }
opt[Int]("lsu-l1-mem-data-width-min") unbounded() action { (v, c) => lsuMemDataWidthMin = v }
opt[Unit]("lsu-l1-coherency") action { (v, c) => lsuL1Coherency = true}
opt[Unit]("with-lsu-bypass") action { (v, c) => withLsuBypass = true }
opt[Unit]("with-iterative-shift") action { (v, c) => withIterativeShift = true }
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30 changes: 29 additions & 1 deletion src/main/scala/vexiiriscv/execute/lsu/Prefetcher.scala
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Expand Up @@ -901,5 +901,33 @@ Slack (VIOLATED) : -0.939ns (required time - arrival time)
-------------------------------------------------------------------
slack -0.939
------------------------------------------------------------------- -------------------
SLICE_X50Y41 FDRE (Prop_fdre_C_Q) 0.456 11.215 r VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_c_pip_ctrl_2_up_SHARED_dirty_reg[3]/Q
net (fo=2, routed) 0.513 11.728 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/logic_ptr_push[1]_i_4_1[3]
SLICE_X50Y41 LUT4 (Prop_lut4_I2_O) 0.124 11.852 r VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/logic_ptr_push[1]_i_5/O
net (fo=1, routed) 0.291 12.143 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/logic_ptr_push[1]_i_5_n_0
SLICE_X51Y43 LUT5 (Prop_lut5_I4_O) 0.124 12.267 f VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/logic_ptr_push[1]_i_4/O
net (fo=2, routed) 0.447 12.714 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/LsuL1Plugin_logic_c_pip_ctrl_2_up_WAYS_HITS_reg[0]
SLICE_X51Y46 LUT3 (Prop_lut3_I0_O) 0.124 12.838 f VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/logic_ptr_push[1]_i_3/O
net (fo=22, routed) 0.691 13.529 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/LsuL1Plugin_logic_c_pip_ctrl_2_up_ALLOW_PROBE_DATA_reg
SLICE_X50Y53 LUT6 (Prop_lut6_I5_O) 0.124 13.653 r VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/LsuL1Plugin_logic_bus_toTilelink_coherent_onC_rspFifo/logic_ram/ram_block_reg_0_1_36_41_i_4/O
net (fo=3, routed) 0.653 14.307 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuL1Plugin_logic_writeback_slots_2_busy_reg
SLICE_X54Y53 LUT6 (Prop_lut6_I0_O) 0.124 14.431 f VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuL1Plugin_logic_ways_3_mem_reg_1_i_38/O
net (fo=137, routed) 0.604 15.035 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuL1Plugin_logic_c_pip_ctrl_2_up_WAYS_HIT_reg_0
SLICE_X59Y53 LUT6 (Prop_lut6_I0_O) 0.124 15.159 f VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuL1Plugin_logic_shared_mem_reg_1_i_18/O
net (fo=5, routed) 0.190 15.348 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuL1Plugin_logic_c_pip_ctrl_2_up_WAYS_HIT_reg
SLICE_X59Y53 LUT2 (Prop_lut2_I1_O) 0.124 15.472 f VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuPlugin_logic_onAddress0_access_waiter_refill[3]_i_3/O
net (fo=10, routed) 0.303 15.776 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuPlugin_logic_onCtrl_traps_l1Failed0
SLICE_X59Y53 LUT3 (Prop_lut3_I2_O) 0.124 15.900 f VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuPlugin_logic_storeBuffer_ops_mem_reg_0_i_96/O
net (fo=3, routed) 0.373 16.272 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/when_LsuPlugin_l6300
SLICE_X58Y53 LUT6 (Prop_lut6_I5_O) 0.124 16.396 r VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/PrefetchRptPlugin_logic_pip_node_1_PROBE_trap_i_2/O
net (fo=4, routed) 0.714 17.110 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/LsuPlugin_logic_storeBuffer_slots_2_valid_reg
SLICE_X47Y47 LUT6 (Prop_lut6_I5_O) 0.124 17.234 f VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram_1/GSharePlugin_logic_mem_counter_reg_i_31/O
net (fo=70, routed) 1.030 18.264 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/early0_DivPlugin_logic_processing_div/FpuUnpackerPlugin_logic_onCvt_asked_reg_1
SLICE_X35Y51 LUT6 (Prop_lut6_I1_O) 0.124 18.388 r VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/early0_DivPlugin_logic_processing_div/ram_block_reg_0_31_0_5_i_13/O
net (fo=1, routed) 0.491 18.879 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/early0_DivPlugin_logic_processing_div/lane0_integer_WriteBackPlugin_logic_write_port_valid
SLICE_X34Y51 LUT2 (Prop_lut2_I1_O) 0.124 19.003 r VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/early0_DivPlugin_logic_processing_div/ram_block_reg_0_31_0_5_i_1__26/O
net (fo=176, routed) 1.142 20.145 VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram/ram_block_reg_0_31_48_53/WE
SLICE_X22Y56 RAMD32 r VexiiRiscvLitex_ae5efec20a1108c1704e91b039083d92/vexiis_0_logic_core/integer_RegFilePlugin_logic_regfile_fpga/asMem_ram/ram_block_reg_0_31_48_53/RAMA/WE
------------------------------------------------------------------- -------------------
*/
4 changes: 4 additions & 0 deletions src/main/scala/vexiiriscv/soc/litex/Soc.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -395,6 +395,8 @@ python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --cpu
--update-repo=no --soc-json build/csr.json --build
--vivado-synth-directive=performanceoptimized --vivado-route-directive=aggressiveexplore
--fetch-l1-mem-data-width-min=128 --lsu-l1-mem-data-width-min=128
python3 -m litex.tools.litex_json2dts_linux build/csr.json --root-device=mmcblk0p2 > build/linux.dts
dtc -o dtb -o build/linux.dtb build/linux.dts
Expand Down Expand Up @@ -662,6 +664,8 @@ perf stat -p $! --timeout 1000 -e r12,r13,r1a,r1b,stalled-cycles-frontend,stalle
perf stat -p $! --timeout 1000 -e r12,r13,r1a,r1b,cycles,instructions,branch-misses,branches
perf stat -p $! --timeout 1000 -e stalled-cycles-frontend,stalled-cycles-backend,cycles,instructions
r8000000000000000,r8000000000000001,r8000000000000004
~/c/libsdl2/libsdl2-2.30.2+dfsg/debian/build-tests# make -j1 check "testsuiteflags=-j1 --verbose" verbose=1 v=1 &> testlog.txt
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