FpuPacker now use Uop spec completion service

SpinalHDL · Apr 26, 2024 · 1b97538 · 1b97538
1 parent 7d03687
commit 1b97538
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Showing 4 changed files with 8 additions and 10 deletions.
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuPackerPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuPackerPlugin.scala
@@ -31,11 +31,11 @@ class FpuPackerPort(_cmd : FpuPackerCmd) extends Area{
 }
 
 class FpuPackerPlugin(val lane: ExecuteLanePlugin,
-                      var wbAt : Int = 3) extends FiberPlugin with CompletionService with RegFileWriterService {
+                      var wbAt : Int = 3) extends FiberPlugin with RegFileWriterService {
   val p = FpuUtils
 
 
-  override def getCompletions(): Seq[Flow[CompletionPayload]] = List(logic.completion)
+//  override def getCompletions(): Seq[Flow[CompletionPayload]] = List(logic.completion)
   override def getRegFileWriters(): Seq[Flow[RegFileWriter]] = List(logic.s3.fpWriter)
 
   val elaborationLock = Retainer()
@@ -55,7 +55,6 @@ class FpuPackerPlugin(val lane: ExecuteLanePlugin,
 
     elaborationLock.await()
 
-    val completion = Flow(CompletionPayload())
     val wbPorts = mutable.LinkedHashMap[Int, Flow[Bits]]()
     val uopsAt = mutable.LinkedHashMap[Int, ArrayBuffer[UopLayerSpec]]()
     for(port <- ports; (uop, at) <- port.uopsAt) uopsAt.getOrElseUpdate(at, ArrayBuffer[UopLayerSpec]()) += uop
@@ -65,6 +64,7 @@ class FpuPackerPlugin(val lane: ExecuteLanePlugin,
       wbPorts(at) = port
       for(uop <- uops) {
         wbp.addMicroOp(port, uop)
+        uop.setCompletion(at+latency)
         uop.reserve(FpuPackerPlugin.this, at)
         ffwbp.addUop(flagsWb, uop, at+latency)
       }
@@ -237,14 +237,9 @@ class FpuPackerPlugin(val lane: ExecuteLanePlugin,
         port.valid := GROUP_OH(i)
         port.payload := fwb.value
       }
-      completion.valid  := valid && GROUP_OH.orR
-      completion.hartId := Global.HART_ID
-      completion.uopId  := Decode.UOP_ID
-      completion.trap   := False
-      completion.commit := True
 
       val fpWriter = Flow(RegFileWriter(FloatRegFile))
-      fpWriter.valid := completion.valid
+      fpWriter.valid := GROUP_OH.orR && valid
       fpWriter.data := fwb.value
       fpWriter.uopId := Decode.UOP_ID
 

diff --git a/src/main/scala/vexiiriscv/regfile/RegFilePlugin.scala b/src/main/scala/vexiiriscv/regfile/RegFilePlugin.scala
@@ -127,7 +127,7 @@ class RegFilePlugin(var spec : RegfileSpec,
       when(!done) {
         port.valid := True
         port.address := counter.resized
-        port.data := 0
+        port.data := spec.initialValue
         counter := counter + 1
       }
     }

diff --git a/src/main/scala/vexiiriscv/riscv/MicroOp.scala b/src/main/scala/vexiiriscv/riscv/MicroOp.scala
@@ -33,6 +33,7 @@ trait RegfileSpec extends Nameable{
   def width : Int
   def x0AlwaysZero : Boolean
   def getName() : String
+  def initialValue : BigInt
 
   def ->(access : RfAccess) = RfResource(this, access)
 }

diff --git a/src/main/scala/vexiiriscv/riscv/RegFile.scala b/src/main/scala/vexiiriscv/riscv/RegFile.scala
@@ -11,6 +11,7 @@ object IntRegFile extends RegfileSpec with AreaObject {
   override def width = Riscv.XLEN
   override def x0AlwaysZero = true
   override def getName() = "integer"
+  override def initialValue: BigInt = 0
 
   def TypeR(key : MaskedLiteral) = SingleDecoding(
     key = key,
@@ -65,6 +66,7 @@ object FloatRegFile extends RegfileSpec with AreaObject {
   override def width = if(Riscv.RVD) 64 else 32
   override def x0AlwaysZero = false
   override def getName() = "float"
+  override def initialValue: BigInt = 0 //if(Riscv.RVD) 0x7FF8000000000000l else 0x7fc00000l
 
   def TypeR(key : MaskedLiteral) = SingleDecoding(
     key = key,