Fix rd.enable sticking high while being in flushed instruction

SpinalHDL · Apr 19, 2024 · 1e9cb02 · 1e9cb02
1 parent ac2313c
commit 1e9cb02
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Showing 7 changed files with 40 additions and 23 deletions.
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -77,6 +77,8 @@ class ParamSimple(){
   var withDiv = false
   var withRva = false
   var withRvf = false
+  var skipFma = false
+  var fpuFmaFullAccuracy = true
   var withRvd = false
   var withRvZb = false
   var privParam = PrivilegedParam.base
@@ -657,7 +659,7 @@ class ParamSimple(){
       plugins += new execute.fpu.FpuUnpackerPlugin(early0)
       plugins += new execute.fpu.FpuAddSharedPlugin(lane0)
       plugins += new execute.fpu.FpuAddPlugin(early0)
-      plugins += new execute.fpu.FpuMulPlugin(early0)
+      plugins += new execute.fpu.FpuMulPlugin(early0, withFma = !skipFma, fmaFullAccuracy = fpuFmaFullAccuracy)
       plugins += new execute.fpu.FpuSqrtPlugin(early0)
       plugins += new execute.fpu.FpuPackerPlugin(lane0)
       //      plugins += new execute.fpu.FpuEmbedded()

diff --git a/src/main/scala/vexiiriscv/execute/ExecuteLanePlugin.scala b/src/main/scala/vexiiriscv/execute/ExecuteLanePlugin.scala
@@ -112,6 +112,7 @@ class ExecuteLanePlugin(override val laneName : String,
       val readCtrl = ctrl(rfReadAt)
 
       val reads = for ((spec, payload) <- rfStageables) yield new Area {
+        setCompositeName(ExecuteLanePlugin.this, s"bypasser_${spec.rf.getName()}_${spec.access.getName()}", weak = false)
         // Implement the register file read
         val rfa = Decode.rfaKeys.get(spec.access)
         val rfPlugin = host.find[RegfileService](_.rfSpec == spec.rf)
@@ -248,6 +249,7 @@ class ExecuteLanePlugin(override val laneName : String,
 
     // Handle SEL initialisation and flushes
     val rp = host[ReschedulePlugin]
+    val rdRfa = Decode.rfaKeys.get(RD)
     for(ctrlId <- 0 to idToCtrl.keys.max){
       ctrl(ctrlId) //Ensure creation
       val c = idToCtrl(ctrlId)
@@ -261,6 +263,7 @@ class ExecuteLanePlugin(override val laneName : String,
           c.upIsCancel := cond
           when(cond) {
             c.bypass(c.LANE_SEL) := False
+            c.bypass(rdRfa.ENABLE) := False
           }
         case None => c.upIsCancel := False
       }

diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala
@@ -12,6 +12,8 @@ import vexiiriscv.riscv._
 
 
 class FpuMulPlugin(val layer : LaneLayer,
+                   withFma : Boolean = true,
+                   fmaFullAccuracy : Boolean = true,
                    var expAt : Int = 0,
                    var normAt: Int = 3,
                    var packAt : Int = 3) extends FiberPlugin{
@@ -29,18 +31,20 @@ class FpuMulPlugin(val layer : LaneLayer,
     val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
-    val addParam = FloatUnpackedParam(
-      exponentMax   = p.unpackedConfig.exponentMax * 2 + 1,
-      exponentMin   = p.unpackedConfig.exponentMin * 2,
-      mantissaWidth = p.unpackedConfig.mantissaWidth * 2 + 1
-    )
     val packParam = FloatUnpackedParam(
       exponentMax   = p.unpackedConfig.exponentMax * 2 + 1,
       exponentMin   = p.unpackedConfig.exponentMin * 2,
       mantissaWidth = p.unpackedConfig.mantissaWidth + 2
     )
+
+    val addParam = FloatUnpackedParam(
+      exponentMax = p.unpackedConfig.exponentMax * 2 + 1,
+      exponentMin = p.unpackedConfig.exponentMin * 2,
+      mantissaWidth = fmaFullAccuracy.mux(p.unpackedConfig.mantissaWidth * 2 + 1, packParam.mantissaWidth)
+    )
+
     val packPort = fpp.createPort(List(packAt), packParam)
-    val addPort = fasp.createPort(List(packAt), addParam, FpuUtils.unpackedConfig)
+    val addPort = withFma generate fasp.createPort(List(packAt), addParam, FpuUtils.unpackedConfig)
 
 
     layer.el.setDecodingDefault(SEL, False)
@@ -71,10 +75,15 @@ class FpuMulPlugin(val layer : LaneLayer,
     val f32 = FORMAT -> FpuFormat.FLOAT
 
     mul(Rvfd.FMUL_S, f32)
-    fma(Rvfd.FMADD_S, f32)
     if(Riscv.RVD) {
       mul(Rvfd.FMUL_D, f64)
-      fma(Rvfd.FMADD_D, f64)
+    }
+
+    if(withFma){
+      fma(Rvfd.FMADD_S, f32)
+      if (Riscv.RVD) {
+        fma(Rvfd.FMADD_D, f64)
+      }
     }
 
 
@@ -140,17 +149,19 @@ class FpuMulPlugin(val layer : LaneLayer,
       packPort.cmd.hartId := Global.HART_ID
       packPort.cmd.uopId := Decode.UOP_ID
 
-      addPort.cmd.at(0) := isValid && SEL && FMA
-      addPort.cmd.rs1.sign := SIGN
-      addPort.cmd.rs1.exponent := EXP
-      addPort.cmd.rs1.mantissa := MAN
-      addPort.cmd.rs1.mode := mode
-      addPort.cmd.rs1.quiet := True
-      addPort.cmd.rs2 := fup(RS3)
-      addPort.cmd.format := FORMAT
-      addPort.cmd.roundMode := FpuUtils.ROUNDING
-      addPort.cmd.hartId := Global.HART_ID
-      addPort.cmd.uopId := Decode.UOP_ID
+      if(withFma) {
+        addPort.cmd.at(0) := isValid && SEL && FMA
+        addPort.cmd.rs1.sign := SIGN
+        addPort.cmd.rs1.exponent := EXP
+        addPort.cmd.rs1.mantissa := MAN.rounded(RoundType.SCRAP)
+        addPort.cmd.rs1.mode := mode
+        addPort.cmd.rs1.quiet := True
+        addPort.cmd.rs2 := fup(RS3)
+        addPort.cmd.format := FORMAT
+        addPort.cmd.roundMode := FpuUtils.ROUNDING
+        addPort.cmd.hartId := Global.HART_ID
+        addPort.cmd.uopId := Decode.UOP_ID
+      }
     }
 
     buildBefore.release()

diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuSqrtPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuSqrtPlugin.scala
@@ -61,7 +61,7 @@ class FpuSqrtPlugin(val layer : LaneLayer,
 
     val onExecute = new layer.Execute(exeAt) {
       val cmdSent = RegInit(False) setWhen (sqrt.io.input.fire) clearWhen (isReady)
-      sqrt.io.input.valid := isValid && SEL && fup.unpackingDone(exeAt )&& !cmdSent
+      sqrt.io.input.valid := isValid && SEL && fup.unpackingDone(exeAt)&& !cmdSent
       sqrt.io.input.a := U(RS1_FP.exponent.raw.lsb ? (B"1" ## RS1_FP.mantissa ## B"0") | (B"01" ## RS1_FP.mantissa))
       sqrt.io.flush := isReady
       sqrt.io.output.ready := False

diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala
@@ -98,7 +98,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0) extends Fiber
       val fsmRsp = unpacker.results(fsmPortId)
       fsmCmd.setIdle()
 
-      val rsValues = rsList.map(rs => this(layer.el(FloatRegFile, rs)))
+      val rsValues = rsList.map(rs => this.up(layer.el(FloatRegFile, rs)))
 
       val fsmRequesters = Bits(rsList.size bits)
       val fsmServed = Bits(rsList.size bits)

diff --git a/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala b/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala
@@ -395,7 +395,7 @@ class DispatchPlugin(var dispatchAt : Int,
       Global.HART_ID := mux(_.ctx.hartId)
       Decode.UOP := mux(_.ctx.uop)
       for(k <- hmKeys) insertNode(k).assignFrom(mux(_.ctx.hm(k)))
-      when(!CtrlLaneApi.LANE_SEL){
+      when(!CtrlLaneApi.LANE_SEL || mux(_.ctx.hm(TRAP))){
         //Allow to avoid having to check the valid down the pipeline
         rdKeys.ENABLE := False
         MAY_FLUSH := False

diff --git a/src/test/scala/vexiiriscv/scratchpad/Synt.scala b/src/test/scala/vexiiriscv/scratchpad/Synt.scala
@@ -67,6 +67,7 @@ object IntegrationSynthBench extends App{
     p.lsuL1Ways = 1
     p.relaxedBranch = true
     p.withRvf = true
+    p.withRvf = true
     p.withMul = true
   }