Add FpuClassPlugin

src/main/scala/vexiiriscv/Param.scala

@@ -664,6 +664,7 @@ class ParamSimple(){
       plugins += new execute.fpu.FpuAddPlugin(early0)
       plugins += new execute.fpu.FpuMulPlugin(early0, withFma = !skipFma, fmaFullAccuracy = fpuFmaFullAccuracy)
       plugins += new execute.fpu.FpuSqrtPlugin(early0)
+      plugins += new execute.fpu.FpuClassPlugin(early0)
       plugins += new execute.fpu.FpuCmpPlugin(early0)
       plugins += new execute.fpu.FpuDivPlugin(early0)
       plugins += new execute.fpu.FpuPackerPlugin(lane0)

src/main/scala/vexiiriscv/execute/fpu/FpuClassPlugin.scala

@@ -0,0 +1,67 @@
+package vexiiriscv.execute.fpu
+
+import spinal.core._
+import spinal.lib.misc.pipeline._
+import spinal.lib.misc.plugin.FiberPlugin
+import vexiiriscv.Global
+import vexiiriscv.decode.Decode
+import vexiiriscv.execute._
+import vexiiriscv.execute.fpu.FpuUtils.{FORMAT, muxDouble}
+import vexiiriscv.riscv.Riscv.RVC
+import vexiiriscv.riscv._
+
+
+class FpuClassPlugin(val layer : LaneLayer,
+                     var wbAt : Int = 0) extends FiberPlugin{
+                       val p = FpuUtils
+                       val SEL = Payload(Bool())
+
+                       val logic = during setup new Area{
+                         val fup = host[FpuUnpackerPlugin]
+                         val iwbp = host.find[IntFormatPlugin](p => p.laneName == layer.laneName)
+                         val buildBefore = retains(layer.el.pipelineLock)
+                         val uopLock = retains(layer.el.uopLock, fup.elaborationLock, iwbp.elaborationLock)
+                         awaitBuild()
+
+                         val iwb = iwbp.access(wbAt)
+
+                         layer.el.setDecodingDefault(SEL, False)
+                         def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
+                           val spec = layer.add(uop)
+                           spec.addDecoding(decodings)
+                           spec.addDecoding(SEL -> True)
+                           iwbp.addMicroOp(iwb, spec)
+                           fup.unpack(uop, RS1)
+                         }
+
+                         add(Rvfd.FCLASS_S, FORMAT -> FpuFormat.FLOAT)
+                         if(Riscv.RVD.get){
+                           add(Rvfd.FCLASS_D, FORMAT -> FpuFormat.DOUBLE)
+                         }
+
+                         uopLock.release()
+
+                         val RS1_FP = fup(RS1)
+
+                         val onWb = new layer.Execute(wbAt) {
+                           val fclassResult = B(0, 10 bits)
+                           val expSubnormal = muxDouble[SInt](FORMAT)(-1023)(-127)
+                           val RS1_FP_SUBNORMAL = fup.getSubnormal(RS1)
+                           fclassResult(0) := RS1_FP.sign && RS1_FP.isInfinity
+                           fclassResult(1) := RS1_FP.sign && RS1_FP.isNormal && !RS1_FP_SUBNORMAL
+                           fclassResult(2) := RS1_FP.sign && RS1_FP.isNormal && RS1_FP_SUBNORMAL
+                           fclassResult(3) := RS1_FP.sign && RS1_FP.isZero
+                           fclassResult(4) := !RS1_FP.sign && RS1_FP.isZero
+                           fclassResult(5) := !RS1_FP.sign && RS1_FP.isNormal && RS1_FP_SUBNORMAL
+                           fclassResult(6) := !RS1_FP.sign && RS1_FP.isNormal && !RS1_FP_SUBNORMAL
+                           fclassResult(7) := !RS1_FP.sign && RS1_FP.isInfinity
+                           fclassResult(8) := RS1_FP.isNan && !RS1_FP.quiet
+                           fclassResult(9) := RS1_FP.isNan && RS1_FP.quiet
+
+                           iwb.valid := SEL
+                           iwb.payload := fclassResult.resized
+                         }
+
+                         buildBefore.release()
+                       }
+                     }

src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala

@@ -28,6 +28,10 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0) extends Fiber
     logic.onUnpack.rs.toList(logic.rsList.toList.indexOf(rs)).RS
   }
 
+  def getSubnormal(rs : RfRead) : Payload[Bool] = {
+    logic.onUnpack.rs.toList(logic.rsList.toList.indexOf(rs)).IS_SUBNORMAL
+  }
+
   def unpackingDone(at : Int) : Bool = at match {
     case unpackAt => !logic.onUnpack.rs.map(_.normalizer.freezeIt).toList.orR
     case _ => True
@@ -135,7 +139,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0) extends Fiber
         val manZero = Bool()
         val expZero = Bool()
         val expOne = Bool()
-        val isSubnormal = expZero && !manZero
+        val IS_SUBNORMAL = insert(expZero && !manZero)
         val recodedExpOffset = UInt(p.exponentWidth bits)
         val recodedExpSub = SInt(p.exponentWidth + 1 bits)
         val expRaw = UInt(p.exponentWidth bits)
@@ -169,7 +173,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0) extends Fiber
         )
         apply(RS) := RS_PRE_NORM
         val normalizer = new Area {
-          val valid = unpackerSel && isSubnormal
+          val valid = unpackerSel && IS_SUBNORMAL
           val asked = RegInit(False) setWhen (fsmRequesters(inputId) && !fsmRequesters.dropLow(inputId + 1).orR) clearWhen (clear)
           val served = RegInit(False) setWhen (fsmRsp.valid && fsmServed.dropLow(inputId + 1).andR) clearWhen (clear)
           fsmRequesters(inputId) := valid && !asked