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67 changes: 67 additions & 0 deletions
67
src/main/scala/vexiiriscv/execute/fpu/FpuClassPlugin.scala
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package vexiiriscv.execute.fpu | ||
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import spinal.core._ | ||
import spinal.lib.misc.pipeline._ | ||
import spinal.lib.misc.plugin.FiberPlugin | ||
import vexiiriscv.Global | ||
import vexiiriscv.decode.Decode | ||
import vexiiriscv.execute._ | ||
import vexiiriscv.execute.fpu.FpuUtils.{FORMAT, muxDouble} | ||
import vexiiriscv.riscv.Riscv.RVC | ||
import vexiiriscv.riscv._ | ||
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class FpuClassPlugin(val layer : LaneLayer, | ||
var wbAt : Int = 0) extends FiberPlugin{ | ||
val p = FpuUtils | ||
val SEL = Payload(Bool()) | ||
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val logic = during setup new Area{ | ||
val fup = host[FpuUnpackerPlugin] | ||
val iwbp = host.find[IntFormatPlugin](p => p.laneName == layer.laneName) | ||
val buildBefore = retains(layer.el.pipelineLock) | ||
val uopLock = retains(layer.el.uopLock, fup.elaborationLock, iwbp.elaborationLock) | ||
awaitBuild() | ||
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val iwb = iwbp.access(wbAt) | ||
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layer.el.setDecodingDefault(SEL, False) | ||
def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = { | ||
val spec = layer.add(uop) | ||
spec.addDecoding(decodings) | ||
spec.addDecoding(SEL -> True) | ||
iwbp.addMicroOp(iwb, spec) | ||
fup.unpack(uop, RS1) | ||
} | ||
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add(Rvfd.FCLASS_S, FORMAT -> FpuFormat.FLOAT) | ||
if(Riscv.RVD.get){ | ||
add(Rvfd.FCLASS_D, FORMAT -> FpuFormat.DOUBLE) | ||
} | ||
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uopLock.release() | ||
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val RS1_FP = fup(RS1) | ||
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val onWb = new layer.Execute(wbAt) { | ||
val fclassResult = B(0, 10 bits) | ||
val expSubnormal = muxDouble[SInt](FORMAT)(-1023)(-127) | ||
val RS1_FP_SUBNORMAL = fup.getSubnormal(RS1) | ||
fclassResult(0) := RS1_FP.sign && RS1_FP.isInfinity | ||
fclassResult(1) := RS1_FP.sign && RS1_FP.isNormal && !RS1_FP_SUBNORMAL | ||
fclassResult(2) := RS1_FP.sign && RS1_FP.isNormal && RS1_FP_SUBNORMAL | ||
fclassResult(3) := RS1_FP.sign && RS1_FP.isZero | ||
fclassResult(4) := !RS1_FP.sign && RS1_FP.isZero | ||
fclassResult(5) := !RS1_FP.sign && RS1_FP.isNormal && RS1_FP_SUBNORMAL | ||
fclassResult(6) := !RS1_FP.sign && RS1_FP.isNormal && !RS1_FP_SUBNORMAL | ||
fclassResult(7) := !RS1_FP.sign && RS1_FP.isInfinity | ||
fclassResult(8) := RS1_FP.isNan && !RS1_FP.quiet | ||
fclassResult(9) := RS1_FP.isNan && RS1_FP.quiet | ||
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iwb.valid := SEL | ||
iwb.payload := fclassResult.resized | ||
} | ||
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buildBefore.release() | ||
} | ||
} |
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