Add prefetch parameters and IntAluPlugin now make from for it.

SpinalHDL · Jun 27, 2024 · 2ceced6 · 2ceced6
1 parent f83fa46
commit 2ceced6
Show file tree

Hide file tree

Showing 6 changed files with 37 additions and 3 deletions.
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -98,6 +98,8 @@ class ParamSimple(){
   var fetchL1Ways = 1
   var fetchL1ReducedBank = false
   var fetchMemDataWidthMin = 32
+  var lsuSoftwarePrefetch = false
+  var lsuHardwarePrefetch = false
   var lsuStoreBufferSlots = 0
   var lsuStoreBufferOps = 0
   var lsuL1Enable = false
@@ -152,6 +154,8 @@ class ParamSimple(){
     lsuStoreBufferSlots = 2
     lsuStoreBufferOps = 32
     withLsuBypass = true
+    lsuSoftwarePrefetch = true
+    lsuHardwarePrefetch = true
 
     //    lsuForkAt = 1
     divArea = false
@@ -307,6 +311,8 @@ class ParamSimple(){
     opt[Int]("lsu-l1-ways") unbounded() action { (v, c) => lsuL1Ways = v }
     opt[Int]("lsu-l1-store-buffer-slots") action { (v, c) => lsuStoreBufferSlots = v }
     opt[Int]("lsu-l1-store-buffer-ops") action { (v, c) => lsuStoreBufferOps = v }
+    opt[Unit]("lsu-hardware-prefetch") action { (v, c) => lsuHardwarePrefetch = true }
+    opt[Unit]("lsu-software-prefetch") action { (v, c) => lsuSoftwarePrefetch = true }
     opt[Int]("lsu-l1-refill-count") action { (v, c) => lsuL1RefillCount = v }
     opt[Int]("lsu-l1-writeback-count") action { (v, c) => lsuL1WritebackCount = v }
     opt[Int]("lsu-l1-mem-data-width-min") action { (v, c) => lsuMemDataWidthMin = v }
@@ -534,6 +540,8 @@ class ParamSimple(){
         storeRs2At = storeRs2Late.mux(2, 0),
         storeBufferSlots = lsuStoreBufferSlots,
         storeBufferOps = lsuStoreBufferOps,
+        hardwarePrefetch = lsuHardwarePrefetch,
+        softwarePrefetch = lsuSoftwarePrefetch,
         translationStorageParameter = MmuStorageParameter(
           levels = List(
             MmuStorageLevel(

diff --git a/src/main/scala/vexiiriscv/execute/IntAluPlugin.scala b/src/main/scala/vexiiriscv/execute/IntAluPlugin.scala
@@ -9,6 +9,7 @@ import spinal.lib.Flow
 import spinal.lib.misc.pipeline._
 import vexiiriscv.Global
 import vexiiriscv.decode._
+import vexiiriscv.execute.lsu.CmoService
 import vexiiriscv.riscv.{Riscv, Rvi}
 
 object IntAluPlugin extends AreaObject {
@@ -37,6 +38,10 @@ class IntAluPlugin(var layer: LaneLayer,
     val abce = AluBitwiseCtrlEnum
 
     val wb = newWriteback(ifp, formatAt)
+    val ORI = (host.get[CmoService] match {
+      case Some(s) => s.withSoftwarePrefetch
+      case None => false
+    }).mux(Rvi.ORI_WO_X0, Rvi.ORI_FULL)
 
     add(Rvi.ADD ).srcs(Op.ADD   , SRC1.RF, SRC2.RF).decode(ALU_CTRL -> ace.ADD_SUB )
     add(Rvi.SUB ).srcs(Op.SUB   , SRC1.RF, SRC2.RF).decode(ALU_CTRL -> ace.ADD_SUB )
@@ -50,7 +55,7 @@ class IntAluPlugin(var layer: LaneLayer,
     add(Rvi.SLTI ).srcs(Op.LESS  , SRC1.RF, SRC2.I).decode(ALU_CTRL -> ace.SLT_SLTU)
     add(Rvi.SLTIU).srcs(Op.LESS_U, SRC1.RF, SRC2.I).decode(ALU_CTRL -> ace.SLT_SLTU)
     add(Rvi.XORI ).srcs(           SRC1.RF, SRC2.I).decode(ALU_CTRL -> ace.BITWISE , ALU_BITWISE_CTRL -> abce.XOR )
-    add(Rvi.ORI  ).srcs(           SRC1.RF, SRC2.I).decode(ALU_CTRL -> ace.BITWISE , ALU_BITWISE_CTRL -> abce.OR  )
+    add(    ORI  ).srcs(           SRC1.RF, SRC2.I).decode(ALU_CTRL -> ace.BITWISE , ALU_BITWISE_CTRL -> abce.OR  )
     add(Rvi.ANDI ).srcs(           SRC1.RF, SRC2.I).decode(ALU_CTRL -> ace.BITWISE , ALU_BITWISE_CTRL -> abce.AND )
 
     add(Rvi.LUI  ).srcs(Op.SRC1, SRC1.U         ).decode(ALU_CTRL -> ace.ADD_SUB)

diff --git a/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala b/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
@@ -45,17 +45,20 @@ class LsuPlugin(var layer : LaneLayer,
                 var withRva : Boolean,
                 var translationStorageParameter: Any,
                 var translationPortParameter: Any,
+                var softwarePrefetch: Boolean,
+                var hardwarePrefetch: Boolean,
                 var addressAt: Int = 0,
                 var triggerAt : Int = 1,
                 var ctrlAt: Int = 2,
                 var wbAt : Int = 2,
                 var storeRs2At : Int = 0,
                 var storeBufferSlots : Int = 0,
-                var storeBufferOps : Int = 0) extends FiberPlugin with DBusAccessService with LsuCachelessBusProvider with LsuService{
+                var storeBufferOps : Int = 0) extends FiberPlugin with DBusAccessService with LsuCachelessBusProvider with LsuService with CmoService{
 
   override def accessRefillCount: Int = 0
   override def accessWake: Bits = B(0)
 
+  override def withSoftwarePrefetch: Boolean = softwarePrefetch
   override def getLsuCachelessBus(): LsuCachelessBus = logic.bus
 
   def busParam = LsuCachelessBusParam(

diff --git a/src/main/scala/vexiiriscv/execute/lsu/Service.scala b/src/main/scala/vexiiriscv/execute/lsu/Service.scala
@@ -3,3 +3,7 @@ package vexiiriscv.execute.lsu
 trait LsuCachelessBusProvider {
   def getLsuCachelessBus() : LsuCachelessBus
 }
+
+trait CmoService{
+  def withSoftwarePrefetch : Boolean
+}
diff --git a/src/main/scala/vexiiriscv/riscv/RegFile.scala b/src/main/scala/vexiiriscv/riscv/RegFile.scala
@@ -21,6 +21,11 @@ object IntRegFile extends RegfileSpec with AreaObject {
     key = key,
     resources = List(RS1, RD).map(this -> _)
   )
+  def TypeI(keys: Seq[MaskedLiteral]) = SingleDecoding(
+    keys = keys,
+    resources = List(RS1, RD).map(this -> _)
+  )
+
   def TypeJ(key : MaskedLiteral) = SingleDecoding(
     key = key,
     resources = List(RD).map(this -> _)

diff --git a/src/main/scala/vexiiriscv/riscv/Rvi.scala b/src/main/scala/vexiiriscv/riscv/Rvi.scala
@@ -30,7 +30,16 @@ object Rvi extends AreaObject {
   val XORI               = TypeI(M"-----------------100-----0010011")
   val SRLI               = TypeI(M"000000-----------101-----0010011")
   val SRAI               = TypeI(M"010000-----------101-----0010011")
-  val ORI                = TypeI(M"-----------------110-----0010011")
+  val ORI_FULL = TypeI(M"-----------------110-----0010011")
+  val ORI_WO_X0 = TypeI(List(
+    M"-----------------1101----0010011",
+    M"-----------------110-1---0010011",
+    M"-----------------110--1--0010011",
+    M"-----------------110---1-0010011",
+    M"-----------------110----10010011",
+  ))
+  def ORI(withHints : Boolean) = withHints.mux(ORI_FULL, ORI_WO_X0)
+
   val ANDI               = TypeI(M"-----------------111-----0010011")