Got a first version of RPT prefetcher to work. WIP

SpinalHDL · Jul 2, 2024 · 65b52ce · 65b52ce
1 parent fe77f16
commit 65b52ce
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Showing 6 changed files with 441 additions and 14 deletions.
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -99,7 +99,7 @@ class ParamSimple(){
   var fetchL1ReducedBank = false
   var fetchMemDataWidthMin = 32
   var lsuSoftwarePrefetch = false
-  var lsuHardwarePrefetch = false
+  var lsuHardwarePrefetch = "none"
   var lsuStoreBufferSlots = 0
   var lsuStoreBufferOps = 0
   var lsuL1Enable = false
@@ -155,8 +155,8 @@ class ParamSimple(){
     lsuStoreBufferSlots = 2
     lsuStoreBufferOps = 32
     withLsuBypass = true
-    lsuSoftwarePrefetch = true
-    lsuHardwarePrefetch = true
+//    lsuSoftwarePrefetch = true
+    lsuHardwarePrefetch = "rpt"
 
     //    lsuForkAt = 1
     divArea = false
@@ -312,7 +312,7 @@ class ParamSimple(){
     opt[Int]("lsu-l1-ways") unbounded() action { (v, c) => lsuL1Ways = v }
     opt[Int]("lsu-l1-store-buffer-slots") action { (v, c) => lsuStoreBufferSlots = v }
     opt[Int]("lsu-l1-store-buffer-ops") action { (v, c) => lsuStoreBufferOps = v }
-    opt[Unit]("lsu-hardware-prefetch") action { (v, c) => lsuHardwarePrefetch = true }
+    opt[String]("lsu-hardware-prefetch") action { (v, c) => lsuHardwarePrefetch = v }
     opt[Unit]("lsu-software-prefetch") action { (v, c) => lsuSoftwarePrefetch = true }
     opt[Int]("lsu-l1-refill-count") action { (v, c) => lsuL1RefillCount = v }
     opt[Int]("lsu-l1-writeback-count") action { (v, c) => lsuL1WritebackCount = v }
@@ -580,8 +580,13 @@ class ParamSimple(){
         bootMemClear = bootMemClear
       )
 
-      if(lsuHardwarePrefetch){
-        plugins += new lsu.PrefetchNextLinePlugin
+      lsuHardwarePrefetch match {
+        case "none" =>
+        case "nl" => plugins += new lsu.PrefetchNextLinePlugin
+        case "rpt" => plugins += new lsu.PrefetchRptPlugin(
+          sets = 128,
+          bootMemClear = bootMemClear
+        )
       }
     }
 

diff --git a/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala b/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
@@ -62,6 +62,7 @@ class LsuPlugin(var layer : LaneLayer,
   override def withSoftwarePrefetch: Boolean = softwarePrefetch
   override def getLsuCachelessBus(): LsuCachelessBus = logic.bus
   override def lsuCommitProbe: Flow[LsuCommitProbe] = logic.commitProbe
+  override def getBlockSize: Int = LsuL1.LINE_BYTES.get
 
   def busParam = LsuCachelessBusParam(
     addressWidth = Global.PHYSICAL_WIDTH,
@@ -786,6 +787,7 @@ class LsuPlugin(var layer : LaneLayer,
       commitProbe.load := l1.LOAD
       commitProbe.store := l1.STORE
       commitProbe.trap := lsuTrap
+      commitProbe.pc := Global.PC
     }
 
     val onWb = new elp.Execute(wbAt){