sync

src/main/scala/vexiiriscv/Param.scala

@@ -167,7 +167,7 @@ class ParamSimple(){
     withMmu = true
     privParam.withSupervisor = true
     privParam.withUser = true
-//    xlen = 64
+    xlen = 64
 
 
     privParam.withDebug = true

src/main/scala/vexiiriscv/misc/Service.scala

@@ -19,7 +19,13 @@ import spinal.core.fiber.Retainer
 	                <0x00005 0x00006 0xFF8>,
 	                <0x00003 0x00004 0xFF8>,
 	                <0x10008 0x10009 0xFF8>;
-        };
+          };
+
+
+          riscv,raw-event-to-mhpmcounters =
+              <0x0000 0x0012 0xffffffff 0xffffffff 0x00000ff8>,
+              <0x0000 0x001a 0xffffffff 0xffffffff 0x00000ff8>;
+
  */
 
 object PerformanceCounterService{

src/main/scala/vexiiriscv/soc/litex/Soc.scala

@@ -447,7 +447,10 @@ https://bbs.archlinux.org/viewtopic.php?id=243100
 https://www.brendangregg.com/perf.html
 perf stat  md5sum /home/miaou/readonly/mp3/01-long_distance_calling-metulsky_curse_revisited.mp3
 perf record md5sum /home/miaou/readonly/mp3/01-long_distance_calling-metulsky_curse_revisited.mp3
+perf record -F 99 -g  -e cpu-clock  md5sum /home/miaou/readonly/mp3/01-long_distance_calling-metulsky_curse_revisited.mp
+
 perf report
+perf report --stdio
 
 video capture => qv4l2
 
@@ -542,7 +545,7 @@ mpg123 -a bluealsa mp3/01-long_distance_calling-metulsky_curse_revisited.mp3
 
 
 perf stat -e branch-misses -e branches -e cache-misses -e cache-references -e L1-icache-loads -e L1-icache-load-misses -e cycles -e instructions ls
-
+-e r1a -e r12
 ~/c/libsdl2/libsdl2-2.30.2+dfsg/debian/build-tests# make -j1 check "TESTSUITEFLAGS=-j1 --verbose" VERBOSE=1 V=1 &> testlog.txt
 
 export DEB_BUILD_OPTIONS="nocheck parallel=4"

src/main/tcl/openocd/dev_rv64gc.tcl

@@ -18,12 +18,12 @@ after 1300
 
 halt
 
-#load_image /media/data2/proj/vexii/litex/debian/Image 0x41000000
+load_image /media/data2/proj/vexii/litex/debian/Image 0x41000000
 load_image /media/data2/proj/vexii/litex/debian/linux.dtb 0x46000000
 load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/opensbi/build/platform/litex/vexriscv/firmware/fw_jump.bin 0x40f00000
 #load_image /media/data2/proj/vexii/litex/debian/opensbi.bin 0x40f00000
 
-
+#bp 0x40f0aa7c 4
 for {set i 0} {$i < $cpu_count} {incr i} {
     targets $_TARGETNAME.$i
     reg pc 0x40f00000

src/main/tcl/openocd/dev_rv64gc_opensbi.tcl

@@ -0,0 +1,30 @@
+
+set cpu_count 1
+if [info exists env(HART_COUNT)]  {
+    set cpu_count $::env(HART_COUNT)
+}
+
+reset halt
+
+targets $_TARGETNAME.0
+resume
+after 1300
+
+halt
+load_image /media/data2/proj/vexii/litex/debian/linux.dtb 0x46000000
+load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/opensbi/build/platform/litex/vexriscv/firmware/fw_jump.bin 0x40f00000
+
+for {set i 0} {$i < $cpu_count} {incr i} {
+    targets $_TARGETNAME.$i
+    reg pc 0x40f00000
+    reg a0 0
+    reg a1 0
+    reg a2 0
+    reg a3 0
+    #resume
+}
+
+
+
+
+

src/test/scala/vexiiriscv/scratchpad/Synt.scala

@@ -559,26 +559,43 @@ object IntegrationSynthBench extends App{
 
 
 
-  //  rtls += Rtl(sc.generateVerilog {
-//    val param = new ParamSimple
-//    import param._
-//    decoders = 1
-//    lanes = 1
-//    regFileSync = false
+  rtls += Rtl(sc.generateVerilog {
+    val param = new ParamSimple
+    import param._
+    decoders = 1
+    lanes = 1
+    regFileSync = false
 //    withGShare = true
 //    withBtb = true
 //    withRas = true
-//    //    withMul = false
-//    //    withDiv = false
-//    withLateAlu = false
-//    allowBypassFrom = 0
-//    relaxedBranch = false
-//    relaxedShift = false
-//    relaxedSrc = true
-//    performanceCounters = 0
-//    withRvc = false
-//    Rtl.ffIo(VexiiRiscv(param.plugins()).setDefinitionName("vexii_1i"))
-//  })
+    fetchL1Enable = true
+    lsuL1Enable = true
+    withMul = true
+    withDiv = true
+    allowBypassFrom = 0
+    relaxedBranch = true
+    Rtl.ffIo(VexiiRiscv(ParamSimple.setPma(param.plugins())).setDefinitionName("vexii_1i_nobtb"))
+  })
+
+  rtls += Rtl(sc.generateVerilog {
+    val param = new ParamSimple
+    import param._
+    decoders = 1
+    lanes = 1
+    regFileSync = false
+    withGShare = true
+    withBtb = true
+    withRas = true
+    withMul = true
+    withDiv = true
+    fetchL1Enable = true
+    lsuL1Enable = true
+    allowBypassFrom = 0
+    relaxedBranch = true
+    relaxedBtb = true
+    Rtl.ffIo(VexiiRiscv(ParamSimple.setPma(param.plugins())).setDefinitionName("vexii_1i"))
+  })
+
 //
 //  rtls += Rtl(sc.generateVerilog {
 //    val param = new ParamSimple
@@ -661,61 +678,61 @@ object IntegrationSynthBench extends App{
 //  })
 
 
-  rtls += Rtl(sc.generateVerilog {
-    val param = new ParamSimple
-    import param._
-    decoders = 1
-    lanes = 1
-    regFileSync = false
-    withGShare = true
-    withBtb = true
-    withRas = true
-    withMul = true
-    withDiv = true
-    divArea = false
-    relaxedBranch = true
-    relaxedBtb = true
-
-    xlen = 64
-    privParam.withSupervisor = true
-    privParam.withUser = true
-    withMmu = true
-    withRva = true
-    withRvf = true
-    withRvd = true
-    fpuFmaFullAccuracy = false
-    withRvc = true
-    withAlignerBuffer = true
-    privParam.withDebug = true
-
-    allowBypassFrom = 0
-    withPerformanceCounters = true
-    additionalPerformanceCounters = 0
-
-    fetchL1Enable = true
-    fetchL1Sets = 64
-    fetchL1Ways = 4
-
-    lsuL1Enable = true
-    lsuL1Sets = 64
-    lsuL1Ways = 4
-    lsuL1RefillCount = 2
-    lsuL1WritebackCount = 2
-    lsuStoreBufferSlots = 2
-    lsuStoreBufferOps = 32
-    lsuL1Coherency = true
-
-
-    val plugins = param.plugins()
-    ParamSimple.setPma(plugins)
-    plugins.foreach{
-      case p : LsuL1Plugin =>
-        p.ackIdWidth = 8
-        p.probeIdWidth = log2Up(p.writebackCount)
-      case _ =>
-    }
-    Rtl.ffIo(VexiiRiscv(plugins).setDefinitionName("vexii_debian"))
-  })
+//  rtls += Rtl(sc.generateVerilog {
+//    val param = new ParamSimple
+//    import param._
+//    decoders = 1
+//    lanes = 1
+//    regFileSync = false
+//    withGShare = true
+//    withBtb = true
+//    withRas = true
+//    withMul = true
+//    withDiv = true
+//    divArea = false
+//    relaxedBranch = true
+//    relaxedBtb = true
+//
+//    xlen = 64
+//    privParam.withSupervisor = true
+//    privParam.withUser = true
+//    withMmu = true
+//    withRva = true
+//    withRvf = true
+//    withRvd = true
+//    fpuFmaFullAccuracy = false
+//    withRvc = true
+//    withAlignerBuffer = true
+//    privParam.withDebug = true
+//
+//    allowBypassFrom = 0
+//    withPerformanceCounters = true
+//    additionalPerformanceCounters = 0
+//
+//    fetchL1Enable = true
+//    fetchL1Sets = 64
+//    fetchL1Ways = 4
+//
+//    lsuL1Enable = true
+//    lsuL1Sets = 64
+//    lsuL1Ways = 4
+//    lsuL1RefillCount = 2
+//    lsuL1WritebackCount = 2
+//    lsuStoreBufferSlots = 2
+//    lsuStoreBufferOps = 32
+//    lsuL1Coherency = true
+//
+//
+//    val plugins = param.plugins()
+//    ParamSimple.setPma(plugins)
+//    plugins.foreach{
+//      case p : LsuL1Plugin =>
+//        p.ackIdWidth = 8
+//        p.probeIdWidth = log2Up(p.writebackCount)
+//      case _ =>
+//    }
+//    Rtl.ffIo(VexiiRiscv(plugins).setDefinitionName("vexii_debian"))
+//  })
 
   val targets = ArrayBuffer[Target]()
   targets ++=  XilinxStdTargets(withFMax = true, withArea = true)