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SpinalHDL · May 21, 2024 · 7aba381 · 7aba381
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Showing 4 changed files with 15 additions and 8 deletions.
diff --git a/ext/SpinalHDL b/ext/SpinalHDL
diff --git a/src/main/scala/vexiiriscv/execute/SimdAddRawPlugin.scala b/src/main/scala/vexiiriscv/execute/SimdAddRawPlugin.scala
@@ -28,19 +28,20 @@ class SimdAddRawPlugin(val layer : LaneLayer) extends FiberPlugin  {
 
     val add4 = layer.add(ADD4)
 
-    val SEL = Payload(Bool())
-    layer.el.setDecodingDefault(SEL, False)
-    val wb = wbp.createPort(at = 0)
-
-    add4.addDecoding(SEL -> True)
     add4.addRsSpec(RS1, executeAt = 0)
     add4.addRsSpec(RS2, executeAt = 0)
-    wbp.addMicroOp(wb, add4)
     add4.setCompletion(0)
 //    add4.mayFlushUpTo(0)
 //    add4.dontFlushFrom(0)
 //    add4.reserve(something, at=0)
 
+    val wb = wbp.createPort(at = 0)
+    wbp.addMicroOp(wb, add4)
+
+    val SEL = Payload(Bool())
+    layer.el.setDecodingDefault(SEL, False)
+    add4.addDecoding(SEL -> True)
+
     earlyLock.release()
 
     //Let's define some logic in the execute lane [0]

diff --git a/src/main/scala/vexiiriscv/soc/demo/MicroSoc.scala b/src/main/scala/vexiiriscv/soc/demo/MicroSoc.scala
@@ -152,7 +152,11 @@ object MicroSocSim extends App{
   }.parse(args, Unit).nonEmpty)
 
 
-  sim.compile(new MicroSoc(p)).doSimUntilVoid("test", seed = 42){dut =>
+  sim.compile(new MicroSoc(p){
+    hardFork{
+      main.ram.thread.logic.mem.simPublic()
+    }
+  }).doSimUntilVoid("test", seed = 42){dut =>
     dut.cd100.forkStimulus()
     dut.asyncReset #= true
     delayed(100 ns)(dut.asyncReset #= false)

diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala
@@ -451,6 +451,8 @@ perf report
 
 video capture => qv4l2
 
+openssl speed -provider legacy -provider default aes-128-cbc
+
 PMU Hardware doesn't support sampling/overflow-interrupts
 
 branch-instructions OR branches                    [Hardware event]