sync before l1 d$ rework/cleaning

SpinalHDL · Jun 27, 2024 · 8f8b3be · 8f8b3be
1 parent 3746ec1
commit 8f8b3be
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/ext/NaxSoftware b/ext/NaxSoftware
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -149,8 +149,8 @@ class ParamSimple(){
     lsuMemDataWidthMin = 64
     lsuL1Sets = 64
     lsuL1Ways = 4
-    lsuL1RefillCount = 2
-    lsuL1WritebackCount = 2
+    lsuL1RefillCount = 4
+    lsuL1WritebackCount = 4
     lsuL1Coherency = false
     lsuStoreBufferSlots = 2
     lsuStoreBufferOps = 32
@@ -176,7 +176,7 @@ class ParamSimple(){
     withMmu = true
     privParam.withSupervisor = true
     privParam.withUser = true
-    xlen = 32
+    xlen = 64
 
 
     privParam.withDebug = true

diff --git a/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala b/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
@@ -702,8 +702,8 @@ class LsuPlugin(var layer : LaneLayer,
 
       val mmuFailure = mmuPageFault || tpk.ACCESS_FAULT || tpk.REDO
       l1.ABORD := FROM_LSU && !PREFETCH && (!isValid || isCancel || pmaL1.rsp.fault || l1.FAULT || mmuFailure || preCtrl.MISS_ALIGNED || withStoreBuffer.mux(wb.loadHazard || fenceTrap.valid, False))
-      ??? PREFETCH / pmaL1 / miss aligned / mmu failure
-      l1.SKIP_WRITE := l1.ATOMIC && !l1.LOAD && scMiss || withStoreBuffer.mux(!FROM_WB && wb.hit || wb.selfHazard, False) || FROM_LSU && onTrigger.HIT || PREFETCH
+      //TODO ??? PREFETCH / pmaL1 / miss aligned / mmu failure
+      l1.SKIP_WRITE := l1.ATOMIC && !l1.LOAD && scMiss || withStoreBuffer.mux(!FROM_WB && wb.hit || wb.selfHazard, False) || FROM_LSU && onTrigger.HIT || FROM_LSU && PREFETCH
 
       if (withStoreBuffer) l1.ABORD setWhen (FROM_WB && wb.selfHazard)