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109 changes: 109 additions & 0 deletions
109
src/main/scala/vexiiriscv/execute/fpu/FpuDivPlugin.scala
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,109 @@ | ||
| package vexiiriscv.execute.fpu | ||
|
|
||
| import spinal.core._ | ||
| import spinal.lib.misc.pipeline._ | ||
| import spinal.lib.misc.plugin.FiberPlugin | ||
| import vexiiriscv.Global | ||
| import vexiiriscv.decode.Decode | ||
| import vexiiriscv.execute._ | ||
| import vexiiriscv.execute.fpu.FpuUtils.FORMAT | ||
| import vexiiriscv.riscv._ | ||
|
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|
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| class FpuDivPlugin(val layer : LaneLayer, | ||
| var exeAt : Int = 0, | ||
| var packAt : Int = 0) extends FiberPlugin{ | ||
| val p = FpuUtils | ||
|
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| val SEL = Payload(Bool()) | ||
|
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| val logic = during setup new Area{ | ||
| val fup = host[FpuUnpackerPlugin] | ||
| val fpp = host[FpuPackerPlugin] | ||
| val dr = host[DivReuse] | ||
| val buildBefore = retains(layer.el.pipelineLock) | ||
| val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock) | ||
| awaitBuild() | ||
|
|
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| val packParam = FloatUnpackedParam( | ||
| exponentMax = p.unpackedConfig.exponentMax-p.unpackedConfig.exponentMin, | ||
| exponentMin = p.unpackedConfig.exponentMin-p.unpackedConfig.exponentMax-1, | ||
| mantissaWidth = p.unpackedConfig.mantissaWidth+2 | ||
| ) | ||
| val packPort = fpp.createPort(List(packAt), packParam) | ||
|
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| layer.el.setDecodingDefault(SEL, False) | ||
| def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = { | ||
| val spec = layer.add(uop) | ||
| spec.addDecoding(SEL -> True) | ||
| spec.addDecoding(decodings) | ||
| uop.resources.foreach { | ||
| case RfResource(_, rs: RfRead) => fup.unpack(uop, rs) | ||
| case _ => | ||
| } | ||
| packPort.uopsAt += spec -> packAt | ||
| } | ||
|
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| add(Rvfd.FDIV_S, FORMAT -> FpuFormat.FLOAT) | ||
| if(Riscv.RVD) { | ||
| add(Rvfd.FDIV_D, FORMAT -> FpuFormat.DOUBLE) | ||
| } | ||
|
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| uopLock.release() | ||
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| val RS1_FP = fup(RS1) | ||
| val RS2_FP = fup(RS2) | ||
| val internalMantissaSize = p.mantissaWidth | ||
| val iterationsWished = 1+internalMantissaSize+2+1 | ||
| val drift = iterationsWished % log2Up(dr.divRadix) | ||
| val interations = iterationsWished + drift | ||
|
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| val onExecute = new layer.Execute(exeAt) { | ||
| when(isValid && SEL) { | ||
| dr.divInject(layer, exeAt, U(B"1" ## RS1_FP.mantissa.raw), U(B"1" ## RS2_FP.mantissa.raw), interations-1) | ||
| } | ||
| val DIVIDER_RSP = insert(dr.divRsp.result(drift+1, iterationsWished bits) | U(dr.divRsp.remain.orR || dr.divRsp.result(0, drift+1 bits).orR).resized) | ||
| } | ||
| import onExecute.DIVIDER_RSP | ||
|
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| val onPack = new layer.Execute(packAt) { | ||
| val needShift = !DIVIDER_RSP.msb | ||
| val mantissa = needShift.mux(DIVIDER_RSP(0, internalMantissaSize+2 bits), DIVIDER_RSP(1, internalMantissaSize+2 bits) | U(DIVIDER_RSP(0)).resized) | ||
| val exponent = RS1_FP.exponent - RS2_FP.exponent - AFix(U(needShift)) | ||
|
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| packPort.cmd.at(0) := isValid && SEL | ||
| packPort.cmd.value.setNormal | ||
| packPort.cmd.value.quiet := False | ||
| packPort.cmd.value.sign := RS1_FP.sign ^ RS2_FP.sign | ||
| packPort.cmd.value.exponent := exponent | ||
| packPort.cmd.value.mantissa := mantissa | ||
| packPort.cmd.format := FORMAT | ||
| packPort.cmd.roundMode := FpuUtils.ROUNDING | ||
| packPort.cmd.hartId := Global.HART_ID | ||
| packPort.cmd.uopId := Decode.UOP_ID | ||
|
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| val forceOverflow = RS1_FP.isInfinity || RS2_FP.isZero | ||
| val infinitynan = RS1_FP.isZero && RS2_FP.isZero || RS1_FP.isInfinity && RS2_FP.isInfinity | ||
| val forceNan = RS1_FP.isNan || RS2_FP.isNan || infinitynan | ||
| val forceZero = RS1_FP.isZero || RS2_FP.isInfinity | ||
|
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| packPort.cmd.flags.NX := False | ||
| packPort.cmd.flags.UF := False | ||
| packPort.cmd.flags.OF := False | ||
| packPort.cmd.flags.DZ := !forceNan && !RS1_FP.isInfinity && RS2_FP.isZero | ||
| packPort.cmd.flags.NV := False | ||
|
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| when(forceNan) { | ||
| packPort.cmd.value.setNanQuiet | ||
| packPort.cmd.flags.NV setWhen((infinitynan || RS1_FP.isNanSignaling || RS2_FP.isNanSignaling)) | ||
| } elsewhen(forceOverflow) { | ||
| packPort.cmd.value.setInfinity | ||
| } elsewhen(forceZero) { | ||
| packPort.cmd.value.setZero | ||
| } | ||
| } | ||
|
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||
| buildBefore.release() | ||
| } | ||
| } |
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