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Dolu1990 committed May 17, 2024
1 parent 8a239d1 commit e42bdb7
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Showing 7 changed files with 122 additions and 7 deletions.
2 changes: 1 addition & 1 deletion ext/NaxSoftware
2 changes: 1 addition & 1 deletion ext/rvls
Submodule rvls updated 1 files
+8 −3 src/hart.cpp
55 changes: 55 additions & 0 deletions src/main/scala/spinal/lib/misc/pipeline/NodeLaneApi.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,55 @@
package spinal.lib.misc.pipeline

import spinal.core._

trait NodeLaneApi{
def nodeLink: Node
def laneName: String
def LANE_SEL: Payload[Bool] = CtrlLaneApi.LANE_SEL

private val _c = nodeLink

def isValid: Bool = _c.isValid
def isReady : Bool = _c.isReady
def isCancel : Bool = _c.isCancel

def apply[T <: Data](that: Payload[T]): T = _c.apply(that, laneName)
def apply[T <: Data](that: Payload[T], subKey : Any): T = _c.apply(that, laneName + "_" + subKey.toString)
def insert[T <: Data](that: T): Payload[T] = {
val p = Payload(that)
apply(p) := that
p
}


abstract class NodeMirror(node : Node) extends NodeBaseApi {
override def valid = node(LANE_SEL, laneName)
override def ready = node.ready
override def cancel = node.cancel
override def isValid: Bool = node(LANE_SEL, laneName)
override def isReady: Bool = node.isReady
override def isFiring = valid && isReady && !isCancel
override def isMoving = valid && (isReady || isCancel)
// override def isCancel: Bool = node.isCancel
override def isCanceling = valid && isCancel
override def apply(key: NamedTypeKey) = ???
override def apply[T <: Data](key: Payload[T]) = node(key, laneName)
override def apply(subKey: Seq[Any]) = ???
def transactionSpawn = valid && !RegNext(valid, False).clearWhen(isReady || isCancel)
}


implicit def stageablePiped2[T <: Data](stageable: Payload[T]): T = this (stageable)
implicit def bundlePimper[T <: Bundle](stageable: Payload[T]): BundlePimper[T] = new BundlePimper[T](this (stageable))
class BundlePimper[T <: Bundle](pimped: T) {
def :=(that: T): Unit = pimped := that
}

class Area(from : NodeLaneApi = this) extends NodeLaneMirror(from)
}

class NodeLaneMirror(from : NodeLaneApi) extends spinal.core.Area with NodeLaneApi {
override def nodeLink: Node = from.nodeLink
override def laneName: String = from.laneName
override def LANE_SEL: Payload[Bool] = from.LANE_SEL
}
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object HeavyLock

class MultithreadedFunSuite(threadCount : Int) extends AnyFunSuite {
val finalThreadCount = if(threadCount > 0) threadCount else {
new oshi.SystemInfo().getHardware.getProcessor.getLogicalProcessorCount
new oshi.SystemInfo().getHardware.getProcessor.getLogicalProcessorCount*4
}
implicit val ec = ExecutionContext.fromExecutorService(
new ForkJoinPool(finalThreadCount, ForkJoinPool.defaultForkJoinWorkerThreadFactory, null, true)
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2 changes: 1 addition & 1 deletion src/main/scala/vexiiriscv/Param.scala
Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ class ParamSimple(){
withMmu = true
privParam.withSupervisor = true
privParam.withUser = true
xlen = 32
xlen = 64


privParam.withDebug = true
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24 changes: 24 additions & 0 deletions src/main/scala/vexiiriscv/soc/litex/Soc.scala
Original file line number Diff line number Diff line change
Expand Up @@ -585,6 +585,30 @@ node-prefetches OR cpu/node-prefetches/
node-prefetch-misses OR cpu/node-prefetch-misses/
Bluetooth :
killall bluealsa
bluealsa -p a2dp-source -p a2dp-sink --a2dp-force-audio-cd
bluetoothctl
connect 88:C9:E8:E6:2A:69
pulseaudio --start
systemctl status bluetooth
speaker-test -t wav -c 6
speaker-test -t wav -c 6 -D btheadset
pacmd list-sinks
aplay -D bluealsa piano2.wave
https://agl-gsod-2020-demo-mkdocs.readthedocs.io/en/latest/icefish/apis_services/reference/audio/audio/bluez-alsa/
systemctl restart bluetooth
pulseaudio-module-bluetooth naaaaa
mpg123 -a bluealsa mp3/01-long_distance_calling-metulsky_curse_revisited.mp3
--sbc-quality=low
perf stat -e branch-misses -e branches -e cache-misses -e cache-references -e L1-icache-loads -e L1-icache-load-misses -e cycles -e instructions ls
~/c/libsdl2/libsdl2-2.30.2+dfsg/debian/build-tests# make -j1 check "TESTSUITEFLAGS=-j1 --verbose" VERBOSE=1 V=1 &> testlog.txt
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42 changes: 39 additions & 3 deletions src/main/tcl/openocd/dev_rv64gc.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -9,15 +9,51 @@ if [info exists env(HART_COUNT)] {
#load_image /media/data2/proj/vexii/litex/buildroot/buildroot/build/rv64gc/images/rootfs.cpio 0x41000000
#load_image /media/data2/proj/vexii/litex/buildroot/opensbi/build/platform/litex/vexriscv/firmware/fw_jump.bin 0x40f00000

load_image /media/data2/proj/vexii/litex/debian/

load_image /media/data2/proj/vexii/litex/debian/Image 0x41000000
reset halt

targets $_TARGETNAME.0
resume
after 1300

halt

#load_image /media/data2/proj/vexii/litex/debian/Image 0x41000000
load_image /media/data2/proj/vexii/litex/debian/linux.dtb 0x46000000
load_image /media/data2/proj/vexii/litex/debian/opensbi.bin 0x40f00000
load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/opensbi/build/platform/litex/vexriscv/firmware/fw_jump.bin 0x40f00000
#load_image /media/data2/proj/vexii/litex/debian/opensbi.bin 0x40f00000


for {set i 0} {$i < $cpu_count} {incr i} {
targets $_TARGETNAME.$i
reg pc 0x40f00000
reg a0 0
reg a1 0
reg a2 0
reg a3 0
resume
}

exit 0

reset halt

targets $_TARGETNAME.0
resume
after 2000

halt

load_image /media/data2/proj/vexii/litex/debian/linux.dtb 0x46000000
load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/opensbi/build/platform/litex/vexriscv/firmware/fw_jump.bin 0x40f00000

reg pc 0x40f00000
reg a0 0
reg a1 0
reg a2 0
reg a3 0
resume




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