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Update SpinalHDL
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@Dolu1990
Dolu1990 committed May 13, 2024
1 parent 839eaf1 commit ef1fa19
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion ext/SpinalHDL
Submodule SpinalHDL updated 81 files
+2 −1 README.md
+8 −0 core/src/main/java/spinal/core/modport.java
+18 −3 core/src/main/scala/spinal/core/AFix.scala
+2 −0 core/src/main/scala/spinal/core/BitVector.scala
+2 −1 core/src/main/scala/spinal/core/BlackBox.scala
+2 −0 core/src/main/scala/spinal/core/Bool.scala
+17 −0 core/src/main/scala/spinal/core/Bundle.scala
+24 −0 core/src/main/scala/spinal/core/Data.scala
+170 −0 core/src/main/scala/spinal/core/Interface.scala
+5 −1 core/src/main/scala/spinal/core/Spinal.scala
+1 −1 core/src/main/scala/spinal/core/Union.scala
+1 −0 core/src/main/scala/spinal/core/core.scala
+22 −8 core/src/main/scala/spinal/core/formal/FormalBootstraps.scala
+2 −1 core/src/main/scala/spinal/core/formal/SymbiYosysBackend.scala
+1 −0 core/src/main/scala/spinal/core/formal/package.scala
+107 −8 core/src/main/scala/spinal/core/internals/ComponentEmitter.scala
+196 −24 core/src/main/scala/spinal/core/internals/ComponentEmitterVerilog.scala
+7 −1 core/src/main/scala/spinal/core/internals/ComponentEmitterVhdl.scala
+14 −4 core/src/main/scala/spinal/core/internals/Expression.scala
+11 −5 core/src/main/scala/spinal/core/internals/Phase.scala
+186 −3 core/src/main/scala/spinal/core/internals/PhaseVerilog.scala
+54 −16 core/src/main/scala/spinal/core/sim/SimBootstraps.scala
+69 −6 core/src/main/scala/spinal/core/sim/package.scala
+38 −3 lib/src/main/scala/spinal/lib/Flow.scala
+50 −15 lib/src/main/scala/spinal/lib/Utils.scala
+2 −2 lib/src/main/scala/spinal/lib/bus/amba3/apb/Apb3CCToggle.scala
+4 −4 lib/src/main/scala/spinal/lib/bus/amba4/axi/sim/Axi4Master.scala
+235 −0 lib/src/main/scala/spinal/lib/bus/amba4/axilite/sim/AxiLite4Master.scala
+1 −2 lib/src/main/scala/spinal/lib/bus/bmb/sim/BmbMemoryAgent.scala
+3 −1 lib/src/main/scala/spinal/lib/bus/bram/BRAM.scala
+1 −1 lib/src/main/scala/spinal/lib/bus/bram/BRAMDecoder.scala
+1 −0 lib/src/main/scala/spinal/lib/bus/bram/BRAMSlaveFactory.scala
+37 −0 lib/src/main/scala/spinal/lib/bus/bram/sim/BRAMDriver.scala
+30 −10 lib/src/main/scala/spinal/lib/bus/misc/BusSlaveFactory.scala
+43 −0 lib/src/main/scala/spinal/lib/bus/regif/BusIfAdapter/BRAMBusInterface.scala
+23 −14 lib/src/main/scala/spinal/lib/bus/regif/BusIfAdapter/WishboneBusInterface.scala
+6 −4 lib/src/main/scala/spinal/lib/bus/regif/BusInterface.scala
+1 −1 lib/src/main/scala/spinal/lib/bus/regif/Document/DocTemplate.scala
+1 −0 lib/src/main/scala/spinal/lib/bus/regif/Document/JsonGenerator.scala
+34 −1 lib/src/main/scala/spinal/lib/bus/wishbone/Wishbone.scala
+42 −37 lib/src/main/scala/spinal/lib/bus/wishbone/WishboneArbiter.scala
+13 −9 lib/src/main/scala/spinal/lib/bus/wishbone/WishboneDecoder.scala
+14 −9 lib/src/main/scala/spinal/lib/bus/wishbone/WishboneIntercon.scala
+6 −6 lib/src/main/scala/spinal/lib/bus/wishbone/WishboneSlaveFactory.scala
+1 −1 lib/src/main/scala/spinal/lib/com/jtag/JtagTapInstructions.scala
+2 −2 lib/src/main/scala/spinal/lib/com/jtag/lattice/ecp5/JtagTapCommands.scala
+5 −0 lib/src/main/scala/spinal/lib/com/jtag/sim/JtagVpi.scala
+4 −2 lib/src/main/scala/spinal/lib/com/usb/ohci/UsbOhci.scala
+7 −3 lib/src/main/scala/spinal/lib/com/usb/ohci/UsbOhciAxi4.scala
+1 −2 lib/src/main/scala/spinal/lib/com/usb/ohci/UsbOhciGenerator.scala
+6 −3 lib/src/main/scala/spinal/lib/com/usb/ohci/UsbOhciWishbone.scala
+9 −4 lib/src/main/scala/spinal/lib/com/usb/phy/UsbHubPhy.scala
+1 −2 lib/src/main/scala/spinal/lib/com/usb/udc/UsbDeviceBmbGenerator.scala
+1 −2 lib/src/main/scala/spinal/lib/com/usb/udc/UsbDeviceWithPhyWishbone.scala
+2 −2 lib/src/main/scala/spinal/lib/eda/altera/QSys.scala
+2 −2 lib/src/main/scala/spinal/lib/fsm/State.scala
+27 −3 lib/src/main/scala/spinal/lib/io/InOutWrapper.scala
+1 −0 lib/src/main/scala/spinal/lib/logic/Decoder.scala
+2 −2 lib/src/main/scala/spinal/lib/memory/sdram/sdr/SdramCtrl.scala
+1 −1 lib/src/main/scala/spinal/lib/sim/bus/wishbone/WishboneDriver.scala
+93 −95 lib/src/main/scala/spinal/lib/system/dma/sg/DmaSg.scala
+15 −2 lib/src/main/scala/spinal/lib/system/dma/sg/MemoryCore.scala
+1 −1 lib/src/main/scala/spinal/lib/system/tag/Bus.scala
+13 −3 sim/src/main/scala/spinal/sim/GhdlBackend.scala
+3 −2 sim/src/main/scala/spinal/sim/VCSBackend.scala
+5 −4 sim/src/main/scala/spinal/sim/VerilatorBackend.scala
+2 −1 sim/src/main/scala/spinal/sim/VpiBackend.scala
+2 −1 tester/src/main/scala/spinal/lib/formal/SpinalFormalFunSuite.scala
+219 −0 tester/src/test/scala/spinal/core/InterfaceTester.scala
+24 −0 tester/src/test/scala/spinal/core/SpinalSimAFixTester.scala
+56 −0 tester/src/test/scala/spinal/lib/UtilsChecker.scala
+10 −0 tester/src/test/scala/spinal/lib/bus/regif/RegIfACC30.scala
+1 −0 tester/src/test/scala/spinal/lib/bus/regif/RegIfBasicAccessTester.scala
+18 −2 tester/src/test/scala/spinal/tester/PlayDev.scala
+18 −0 tester/src/test/scala/spinal/tester/code/Formal.scala
+2 −2 tester/src/test/scala/spinal/tester/scalatest/FormalSimpleTester.scala
+73 −0 tester/src/test/scala/spinal/tester/scalatest/IsUnknownTester.scala
+20 −0 tester/src/test/scala/spinal/tester/scalatest/SpinalSimLibTester.scala
+92 −0 tester/src/test/scala/spinal/tester/scalatest/SpinalSimWishboneBusInterfaceTester.scala
+20 −20 tester/src/test/scala/spinal/tester/scalatest/SpinalSimWishboneSimTester.scala
+52 −22 tester/src/test/scala/spinal/tester/scalatest/SpinalSimWishboneSlaveFactoryTester.scala

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