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Issues: fabianschuiki/moore

Fully compile the PULP common_cells
#136 opened May 2, 2020 by fabianschuiki
Open
Is there a plan to implent moore in c++?
#233 by hunterzju was closed Nov 13, 2021
Closed 2
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82 Open 143 Closed
82 Open 143 Closed
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Issues list

How to use Moore to covert VHDL?
#253 opened Apr 10, 2024 by HNULiMingyuan
Build fails due to type deduction
#251 opened May 24, 2023 by snarlawar123
3
Build fails due to missing Standard.h file in mlir-c/Dialect
#250 opened Feb 22, 2023 by vani2620
2
Desync between cargo build and repo.
#248 opened Aug 1, 2022 by samerogers
2
Failing to build on Mac
#245 opened Jul 12, 2022 by gussmith23
4
Build and Install problems in moore
#244 opened Apr 20, 2022 by DeepFlyingSky
5
Is there a plan to support System Verilog features like Classes/Constraints/Interfaces?
#239 opened Mar 15, 2022 by jainamq
1
Eliminate HIR in favor of AST-specific queries A-hir Area: High-level Intermediate Representation. L-vlog Language: Verilog and SystemVerilog.
#237 opened Jan 21, 2022 by fabianschuiki
2 tasks
Remove legacy LLHD crate codegen and dependency A-codegen Area: Code generation. A-deps Area: Dependencies. C-cleanup Category: Clean up or refactor code.
#236 opened Nov 21, 2021 by fabianschuiki
1 of 3 tasks
Add Moore MIR dialect and move codegen to CIRCT A-codegen Area: Code generation. C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog. P-high Priority: High.
#235 opened Nov 21, 2021 by fabianschuiki
1 of 6 tasks
9
problems about ports when build in hierachy A-mir Area: Mid-level Intermediate Representation. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog. P-high Priority: High.
#231 opened Sep 8, 2021 by Zhangyanting-1997
1
Consider adding support for importing / exporting UHDM C-enhancement Category: Adding or improving on features.
#229 opened Aug 17, 2021 by mithro
1
Non-constant case item not supported A-codegen Area: Code generation. C-bug Category: This is a bug. E-help-wanted Call for Participation: Help wanted on this issue. L-vlog Language: Verilog and SystemVerilog.
#227 opened Jun 16, 2021 by zyedidia
1
Declare module names in a separate namespace A-resolve Area: Name resolution. C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
#226 opened Apr 1, 2021 by fabianschuiki
Add option to treat unknown modules as external C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
#225 opened Mar 30, 2021 by fabianschuiki
lvalue lowering of cast to logic [31:0] not yet supported
#223 opened Feb 3, 2021 by mdko
1
Emit assert/assume as call to llhd.assert intrinsic A-codegen Area: Code generation. C-enhancement Category: Adding or improving on features. E-easy Call for Participation: Easy issue, good first issue. L-vlog Language: Verilog and SystemVerilog.
#222 opened Jan 9, 2021 by fabianschuiki
Wait with unit-less duration generates incorrect code A-codegen Area: Code generation. A-typeck Area: Type checking, inference, and computation. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog.
#220 opened Jan 9, 2021 by fabianschuiki
Add query derive attribute for equality-by-pointer C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
#214 opened Nov 7, 2020 by fabianschuiki
Switch to codespan crate C-enhancement Category: Adding or improving on features. P-long-term Priority: Long-term endeavour.
#212 opened Nov 3, 2020 by fabianschuiki
Implement RST visitor C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
#211 opened Oct 31, 2020 by fabianschuiki
Factor mir rvalue/lvalue builders into one single builder A-mir Area: Mid-level Intermediate Representation. C-cleanup Category: Clean up or refactor code. E-easy Call for Participation: Easy issue, good first issue. L-vlog Language: Verilog and SystemVerilog.
#209 opened Oct 26, 2020 by fabianschuiki
Questions about moore-vhdl-syntax
#203 opened Jul 23, 2020 by m-kru
2
Canonicalize param env before codegen A-codegen Area: Code generation. C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
#187 opened Jun 13, 2020 by fabianschuiki
3 tasks
Add typeck query that fully checks a design A-typeck Area: Type checking, inference, and computation. C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
#184 opened Jun 7, 2020 by fabianschuiki
ProTip! no:milestone will show everything without a milestone.