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[ESIMD][NFC] Rework the L1/L2 cache hints passing across internal funcs #12899

Merged
merged 4 commits into from
Mar 5, 2024
Merged

[ESIMD][NFC] Rework the L1/L2 cache hints passing across internal funcs #12899

merged 4 commits into from
Mar 5, 2024

Commits on Mar 5, 2024

  1. [ESIMD][NFC] Rework the L1/L2 cache hints passing across internal funcs 

    Cache-hints:
* cache_hint and cache_level were also moved to memory_properties.hpp
* added check_cache_hints() function accepting PropertyListT instead of
  L1/L2 template parameters.

Restructures in block_Load:
* block_load_impl() functions now accept template param PropertyListT
  instead of L1H, L2H and alignment FlagsT.
* only block_load_impl functions call check_cache_hints() now.
* Replaced the uses of lsc.load.stateless with lsc.load.merge.stateless
  It does not change the GPU code-gen, it is identical.

Signed-off-by: Klochkov, Vyacheslav N <vyacheslav.n.klochkov@intel.com>
    @v-klochkov
    v-klochkov committed Mar 5, 2024
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  2. [ESIMD][NFC] Pass PropertyListT to block_store_impl() instead of L1,L… 

    …2 and FlagsT

Signed-off-by: Klochkov, Vyacheslav N <vyacheslav.n.klochkov@intel.com>
    @v-klochkov
    v-klochkov committed Mar 5, 2024
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  3. Merge remote-tracking branch 'intel_llvm/sycl' into esimd_L1_L2_rewor… 

    …k_L3_assert
    @v-klochkov
    v-klochkov committed Mar 5, 2024
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  4. Merge remote-tracking branch 'intel_llvm/sycl' into esimd_L1_L2_rewor… 

    …k_L3_assert
    @v-klochkov
    v-klochkov committed Mar 5, 2024
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