[ESIMD][NFC] Rework the L1/L2 cache hints passing across internal funcs

sycl/include/sycl/ext/intel/esimd/common.hpp

@@ -13,6 +13,7 @@
 #include <sycl/detail/defines.hpp>
 #include <sycl/exception.hpp>
 #include <sycl/ext/intel/esimd/detail/defines_elementary.hpp>
+#include <sycl/ext/intel/esimd/memory_properties.hpp>
 #include <sycl/ext/intel/esimd/native/common.hpp>
 
 #include <cstdint> // for uint* types
@@ -344,46 +345,6 @@ template <__ESIMD_NS::native::lsc::atomic_op Op> constexpr int get_num_args() {
 
 } // namespace detail
 
-/// L1, L2 or L3 cache hints.
-enum class cache_hint : uint8_t {
-  none = 0,
-  /// load/store/atomic: do not cache data to cache;
-  uncached = 1,
-
-  // load: cache data to cache;
-  cached = 2,
-
-  /// store: write data into cache level and mark the cache line as "dirty".
-  /// Upon eviction, the "dirty" data will be written into the furthest
-  /// subsequent cache;
-  write_back = 3,
-
-  /// store: immediately write data to the subsequent furthest cache, marking
-  /// the cache line in the current cache as "not dirty";
-  write_through = 4,
-
-  /// load: cache data to cache using the evict-first policy to minimize cache
-  /// pollution caused by temporary streaming data that may only be accessed
-  /// once or twice;
-  /// store/atomic: same as write-through, but use the evict-first policy
-  /// to limit cache pollution by streaming;
-  streaming = 5,
-
-  /// load: asserts that the cache line containing the data will not be read
-  /// again until it’s overwritten, therefore the load operation can invalidate
-  /// the cache line and discard "dirty" data. If the assertion is violated
-  /// (the cache line is read again) then behavior is undefined.
-  read_invalidate = 6,
-
-  // TODO: Implement the verification of this enum in check_cache_hint().
-  /// load, L2 cache only, next gen GPU after Xe required: asserts that
-  /// the L2 cache line containing the data will not be written until all
-  /// invocations of the shader or kernel execution are finished.
-  /// If the assertion is violated (the cache line is written), the behavior
-  /// is undefined.
-  const_cached = 7
-};
-
 /// The scope that fence() operation should apply to.
 /// Supported platforms: DG2, PVC
 enum class fence_scope : uint8_t {
@@ -440,9 +401,6 @@ enum class memory_kind : uint8_t {
   local = 3, /// shared local memory
 };
 
-/// L1, L2 or L3 cache hint levels. L3 is reserved for future use.
-enum class cache_level : uint8_t { L1 = 1, L2 = 2, L3 = 3 };
-
 namespace detail {
 
 /// Data size or format to read or store
@@ -632,6 +590,26 @@ void check_cache_hint() {
   }
 }
 
+template <typename PropertyListT> constexpr bool has_cache_hints() {
+  constexpr cache_hint L1H =
+      getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
+  constexpr cache_hint L2H =
+      getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
+  return L1H != cache_hint::none || L2H != cache_hint::none;
+}
+
+// Currently, this is just a wrapper around 'check_cache_hint' function.
+// It accepts the compile-time properties that may include cache-hints
+// to be verified.
+template <cache_action Action, typename PropertyListT>
+void check_cache_hints() {
+  constexpr cache_hint L1H =
+      getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
+  constexpr cache_hint L2H =
+      getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
+  check_cache_hint<Action, L1H, L2H>();
+}
+
 constexpr lsc_data_size expand_data_size(lsc_data_size DS) {
   if (DS == lsc_data_size::u8)
     return lsc_data_size::u8u32;