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Sonata support #86

Merged
merged 9 commits into from
Jan 25, 2024
Merged

Sonata support #86

merged 9 commits into from
Jan 25, 2024

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GregAC
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@GregAC GregAC commented Jan 10, 2024

Haven't done loads of testing but this broadly works, existing LCD demo can use the screen (noting the v0.2 board needs a mod to turn on the backlight: newaetech/sonata-pcb#9) without any modifications.

Longer term we may want some kind of 'board ID' peripheral so software knows what it's running on but not needed for this initial work.

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GregAC commented Jan 10, 2024

@colinoflynn, @jpcrypt please note may be useful to you for bring up work.

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GregAC commented Jan 10, 2024

OpenOCD/GDB is also working, the tcl file you need is included in the PR, you'll want to alter load_demo_system.sh to use it rather than the arty one.

marnovandermaas
marnovandermaas reviewed Jan 11, 2024
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Very useful work. Some of this will need to be ported over to this PR: lowRISC/sonata-system#14

I will test this PR before approving once I get access to a board.

dv/verilator/demo_system_verilator_lint.vlt
Comment on lines +27 to +28
lint_off -rule UNOPTFLAT -file "*/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv"
lint_off -rule WIDTHEXPAND -file "*pulp_riscv_dbg/src/dm_mem.sv"
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Can you put a comment in here on why you need to turn these lints off?

ibex_demo_system_core.core
@@ -21,7 +22,12 @@ filesets:
- rtl/system/spi_top.sv
file_type: systemVerilogSource

files_lint_verilator:
files:
- lint/verilator_waiver.vlt: {file_type: vlt}
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Should this point to the demo_system_verilator_lint.vlt file created in this commit?

rtl/system/jtag_id_pkg.sv Outdated Show resolved Hide resolved
rtl/fpga/top_sonata.sv Outdated Show resolved Hide resolved
marnovandermaas
marnovandermaas approved these changes Jan 15, 2024
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I have tested this PR and it work on my Sonata board (revision 0.2). I made a few changes:

  • Added SW5 as a reset button.
  • Cleaned up XDC and top files.
  • Added Sonata instructions to the README.
  • Modified the load script to accept TCL file as argument.

I've approved this PR, but I will let someone else merge it since I made some modifications.

GregAC added 6 commits January 16, 2024 14:12
@GregAC @marnovandermaas
Update riscv_dbg patches for latest version
d638f10
@GregAC @marnovandermaas
Update pulp_riscv_dbg to pulp-platform/riscv-dbg@138d74b
d391e6f 
Update code from upstream repository https://github.com/pulp-
platform/riscv-dbg to revision
138d74bcaa90c70180c12215db3776813d2a95f2

* Update CHANGELOG.md (bluew)
* dm_csrs: Fix W1C behavior of `sberror` (Andreas Kurth)
* Add `xprop_off` to Xprop-incompatible processes (Andreas Kurth)
* debug_rom/gen_rom.py: Fix TypeError (Andreas Kurth)
* debug_rom/gen_rom.py: Fix indentation in p_outmux (Andreas Kurth)
* debug_rom/Makefile: Explicitly invoke `python3` (Andreas Kurth)
* Update CHANGELOG.md (bluew)
* tb: Handle unset VCS_HOME and VSIM_HOME seamlessly (bluew)
* tb: Simplify default tooling names (bluew)
* tb: Tie dangling ports (bluew)
* Update documentation (Christopher Reinwardt)
* [fix] Realign addresses to 64-bit (Christopher Reinwardt)
* Update CHANGELOG.md (bluew)
* tb: Ignore comb warnings (bluew)
* dmi_jtag: Update `dmi` `op` field based on DMI response (Andreas
  Kurth)
* dmi_jtag: Add mechanism for capturing failed DM op (Andreas Kurth)
* dmi_jtag: Set busy error only if no sticky error is set (Andreas
  Kurth)
* tb: Fix make vcsify (bluew)
* tb: Rewrite buggy openocd test script in Python (bluew)
* tb/Makefile: Use tabs (bluew)
* tb: Fix testbench build (bluew)
* dm_mem: Clear state of hart upon ndmreset (Andreas Kurth)
* dmi_jtag_tap: Bring all state to initial value in Test-Logic-Reset
  (Andreas Kurth)
* dmi_jtag: Take DMI response into account for reads (Andreas Kurth)
* dm_csrs: Return busy DMI response if SBA is busy (Andreas Kurth)
* dm_csrs: Return busy DMI response if command is busy (Andreas Kurth)
* dm_csrs: Put entire `dmi_resp_o` through FIFO (Andreas Kurth)
* dmi_jtag_tap: Use generic tech cells (Luca Colagrande)
* jtag_test: Add `read_dmi_exp_backoff()` and `sba_read_double()`
  functions (Luca Colagrande)
* Fix r/s/t/u-reset commands (epsilon)
* Update CHANGELOG.md (bluew)
* Re-align pins of dmi_bscane_tap with dmi_jtag_tap (Noah Huetter)
* Update CHANGELOG.md (bluew)
* Update changelog (Manuel Eggimann)
* Update JTAG Test package to reflect TestLogicReset fix (Manuel
  Eggimann)
* Make dmi_rst_ni synchronous in dm_csrs & filter glitches on
  dmi_rst_no (Manuel Eggimann)
* Bump to latest common cells version and add missing cdc port signals
  (Manuel Eggimann)
* Actually reset the dmi on remote_bitbang request (Manuel Eggimann)
* Modify tb to issue random dmi resets between transactions (Manuel
  Eggimann)
* Fix jtag DV IP to reset ir_select reg during reset (Manuel Eggimann)
* Fix wrong async reset connection and fix wrong dmi_clear logic
  (Manuel Eggimann)
* Fix syntax errors (Manuel Eggimann)
* Point to draft PR in common_cells for clearable CDC IPs (Manuel
  Eggimann)
* First draft of dmihardreset support and proper warm reset capability
  (Manuel Eggimann)
* Update CHANGELOG.md (bluew)
* [dm_sba] Fix verilator and ascentlint warnings (Michael Schaffner)
* [dm_sba] Move address increment arith out of the FSM (Michael
  Schaffner)
* [dm_sba/dm_csrs] Implement 'bad address' and 'other' error codes
  (Michael Schaffner)
* [dm_csrs] Correct reset value of sbcs register (Michael Schaffner)
* Address code review nits (Florian Zaruba)
* doc: Update documentation with OpenOCD configuration (Florian
  Zaruba)
* Add Xilinx BSCANE2 tap (Florian Zaruba)
* Revert "Merge pull request pulp-platform/riscv-dbg#111 from pulp-
  platform/feature/dmi-bscane" (bluew)
* sba: fix sberror reporting, [3] for unaligned access and [4] for
  unsupported size (Tzachi Noy)
* sba: shift sbdata_o accoring to be_idx for partial reads
  (sbacces8/16/...) (Tzachi Noy)
* sba: shift master_wdata_o to be aligned with master_be_o (Tzachi
  Noy)
* make sbaccess field writeable, and set value of
  sbacces8/16/32/64/128 according to BusWidth (Tzachi Noy)
* Fix for 64-bit accesses (Arjan Bink)
* Alternative fix for pull request 27 (Arjan Bink)

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
@GregAC @marnovandermaas
[vendor] Vendor OT primitives directly
910efd3
@GregAC @marnovandermaas
Update lowrisc_ibex to lowRISC/ibex@c9f4a329
0533bb8 
Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
c9f4a329636e59acb10647333badbb31bc7512b8

* [ci] introduce GitHub actions based private CI (Gary Guo)
* [rtl] Fix FI vulnerability in RF (Pascal Nasahl)
* [doc] Update cosim version (Pascal Nasahl)

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
@GregAC @marnovandermaas
Update lowrisc_ip to lowRISC/opentitan@042415198f
53ef0a6 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
042415198f3dc6b3bc387c669c7e9cf982d208e2

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
@GregAC @marnovandermaas
Add option to use JTAG TAP over BSCANE TAP
8bab9d6 
This allows use of JTAG on systems with physical JTAG ports rather than
using the internal Xilinx BSCANE primitive.
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The last force push was a rebasing on top of the formatting fixes that have been merged.

alees24
alees24 approved these changes Jan 17, 2024
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Looks good, thanks for all this. I've been using the Sonata build successfully for a number of days, excepting the debug access which I have not yet tried.

GregAC and others added 3 commits January 18, 2024 15:18
@GregAC @marnovandermaas
Add initial Sonata board support
7aeb084 
This includes:
- Pin definitions in XDC file
- Modified build rules for FuseSoC
- A clock generator
- A top-level for Sonata
- A TCL file for Sonata

Co-authored-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
@marnovandermaas
Modify load script to allow specifying TCL
8701a7d 
This is useful when wanting to program the Sonata board, which can now
be done using the following command:
```sh
./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo ./util/sonata-openocd-cfg.tcl
```
@marnovandermaas
Add Sonata instructions to README
9795195
marnovandermaas added a commit to marnovandermaas/sonata-system that referenced this pull request Jan 18, 2024
@marnovandermaas
Add support for Sonata PCB
1946ed6 
This commit assumes revision 0.2 of the board. It adds a pin file, a top
level module, a clock generator and the appropriate changes to the core
file. It also updates the getting started guide to use the Sonata PCB by
default.

This commit is derived from a PR in the demo system:
lowRISC/ibex-demo-system#86
@marnovandermaas marnovandermaas mentioned this pull request Jan 18, 2024
Merged
@marnovandermaas marnovandermaas merged commit 2039880 into lowRISC:main Jan 25, 2024
2 checks passed
marnovandermaas added a commit to marnovandermaas/sonata-system that referenced this pull request Feb 2, 2024
@marnovandermaas
Add support for Sonata PCB
24a964d 
This commit assumes revision 0.2 of the board. It adds a pin file, a top
level module, a clock generator and the appropriate changes to the core
file. It also updates the getting started guide to use the Sonata PCB by
default.

This commit is derived from a PR in the demo system:
lowRISC/ibex-demo-system#86
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@alees24 alees24 alees24 approved these changes

@marnovandermaas marnovandermaas marnovandermaas approved these changes

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@GregAC @marnovandermaas @alees24