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Pass artifacts over process
lint #292: Commit 8a833f7 pushed by Scheremo
August 22, 2024 15:00 58s scheremo/CIMirror
August 22, 2024 15:00 58s
Another CI iteration...
lint #291: Commit e9d3f3c pushed by Scheremo
August 22, 2024 14:52 53s scheremo/CIMirror
August 22, 2024 14:52 53s
Update CI scripts
lint #290: Commit 178b89b pushed by Scheremo
August 22, 2024 14:36 2m 2s scheremo/convolveIntegration
August 22, 2024 14:36 2m 2s
Update CI scripts
lint #289: Commit e9f5f98 pushed by Scheremo
August 22, 2024 14:28 52s scheremo/convolveIntegration
August 22, 2024 14:28 52s
Bring up CI on gitlab mirrors
lint #288: Commit 2afd04e pushed by Scheremo
August 22, 2024 13:49 54s scheremo/convolveIntegration
August 22, 2024 13:49 54s
FPGA: Create FPGA target and initial padframe
lint #287: Commit b5fb695 pushed by sermazz
August 22, 2024 12:14 1m 0s smazzola/fpga-target
August 22, 2024 12:14 1m 0s
Update all dependencies on TUE server
lint #286: Commit 95d7a90 pushed by Scheremo
August 22, 2024 12:08 1m 4s 22082024
August 22, 2024 12:08 1m 4s
Update all dependencies on TUE server
lint #285: Commit 95d7a90 pushed by Scheremo
August 22, 2024 12:08 1m 9s scheremo/convolveIntegration
August 22, 2024 12:08 1m 9s
Improve makefile flow (#28)
lint #284: Commit 8c5a506 pushed by Scheremo
August 21, 2024 14:15 1m 11s devel
August 21, 2024 14:15 1m 11s
lint
lint #283: by sermazz
August 21, 2024 08:27 1m 2s smazzola/make-flow
August 21, 2024 08:27 1m 2s
Update KUL IP
lint #282: Commit 387cd66 pushed by Scheremo
August 20, 2024 13:47 50s scheremo/convolveIntegration
August 20, 2024 13:47 50s
Enumerate external registers in package
lint #280: Commit ab457a2 pushed by Scheremo
August 20, 2024 13:12 58s scheremo/hyper
August 20, 2024 13:12 58s
Fix typo
lint #279: Commit 0fb51a4 pushed by Scheremo
August 20, 2024 11:57 52s scheremo/hyper
August 20, 2024 11:57 52s
Hyperbus WIP
lint #278: Commit 860f15f pushed by Scheremo
August 20, 2024 11:56 55s scheremo/hyper
August 20, 2024 11:56 55s
Hyperbus WIP
lint #277: Commit 76d58ba pushed by Scheremo
August 20, 2024 11:54 50s scheremo/hyper
August 20, 2024 11:54 50s
Add APB ports for external registers (#33)
lint #276: Commit b2291c6 pushed by Lore0599
August 20, 2024 09:44 49s devel
August 20, 2024 09:44 49s
Add APB ports for external registers
lint #275: Commit 7a216cc pushed by Lore0599
August 20, 2024 09:42 1m 5s lleone/asic-target
August 20, 2024 09:42 1m 5s
Changed Pads Regs and FLL regs addres map
lint #274: Commit 50c3007 pushed by Lore0599
August 20, 2024 09:24 59s lleone/asic-target
August 20, 2024 09:24 59s
Changed address map again
lint #273: Commit 76b99f5 pushed by Lore0599
August 20, 2024 09:23 1m 1s lleone/asic-target
August 20, 2024 09:23 1m 1s
Changed Pads Regs and FLL regs addres map
lint #272: Commit 7ca68dd pushed by Lore0599
August 20, 2024 09:19 54s lleone/asic-target
August 20, 2024 09:19 54s
Add APB ports for external registers
lint #271: Commit e02ecf8 pushed by Lore0599
August 19, 2024 17:58 53s lleone/asic-target
August 19, 2024 17:58 53s
Format verible
lint #270: Commit f9bc183 pushed by Lore0599
August 19, 2024 17:57 57s lleone/asic-target
August 19, 2024 17:57 57s
Add APB ports for external registers
lint #269: Commit 58ac731 pushed by Lore0599
August 19, 2024 17:50 53s lleone/asic-target
August 19, 2024 17:50 53s
HW: Refactor Cluster integration (#24)
lint #268: Commit 9d5c562 pushed by Lore0599
August 19, 2024 16:41 49s lleone/asic-target
August 19, 2024 16:41 49s