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[WIP] hw: Integrate PULP Cluster in Cluster domain (not compiling atm)
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@sermazz
sermazz committed Sep 10, 2024
1 parent 2514c50 commit 52e7a01
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305 changes: 225 additions & 80 deletions hw/chimera_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -160,6 +160,108 @@ module chimera_cluster

end

////////////////////////////////////////////////////////////////////////
// Complement chimera_cluster_adapter with CDC slice for PULP cluster //
////////////////////////////////////////////////////////////////////////
`include "axi/assign.svh"
`include "axi/typedef.svh"
//TODO(smazzola): move all of this in a customized cluster adapter for PULP Cluster

// SoC to Cluster CDC source slice (narrow slave)
AXI_BUS #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth )
) soc_to_cluster_axi_bus();
AXI_BUS_ASYNC_GRAY #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) async_soc_to_cluster_axi_bus();

axi_cdc_src_intf #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) soc_to_cluster_src_cdc_fifo_i (
.src_clk_i ( soc_clk_i ),
.src_rst_ni ( rst_ni ),
.src ( soc_to_cluster_axi_bus ),
.dst ( async_soc_to_cluster_axi_bus )
);

`AXI_ASSIGN_FROM_REQ(soc_to_cluster_axi_bus, clu_axi_adapter_slv_req)
`AXI_ASSIGN_TO_RESP(clu_axi_adapter_slv_resp, soc_to_cluster_axi_bus)

// Cluster to SoC CDC destination slice (narrow master)
AXI_BUS #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth )
) cluster_to_soc_axi_bus();
AXI_BUS_ASYNC_GRAY #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) async_cluster_to_soc_axi_bus();

axi_cdc_dst_intf #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) cluster_to_soc_dst_cdc_fifo_i (
.dst_clk_i ( clu_clk_i ),
.dst_rst_ni ( rst_ni ),
.src ( async_cluster_to_soc_axi_bus ),
.dst ( cluster_to_soc_axi_bus )
);

`AXI_ASSIGN_TO_REQ(clu_axi_adapter_mst_req, cluster_to_soc_axi_bus)
`AXI_ASSIGN_FROM_RESP(cluster_to_soc_axi_bus, clu_axi_adapter_mst_resp)

// DMA CDC destination slice (wide master)
AXI_BUS #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( WideDataWidth ),
.AXI_ID_WIDTH ( WideMasterIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth )
) dma_axi_bus();
AXI_BUS_ASYNC_GRAY #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( WideDataWidth ),
.AXI_ID_WIDTH ( WideMasterIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) async_dma_axi_bus();

axi_cdc_dst_intf #(
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_WIDTH ( WideDataWidth ),
.AXI_ID_WIDTH ( WideMasterIdWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) dma_dst_cdc_fifo_i (
.dst_clk_i ( clu_clk_i ),
.dst_rst_ni ( rst_ni ),
.src ( async_dma_axi_bus ),
.dst ( dma_axi_bus )
);

`AXI_ASSIGN_TO_REQ(clu_axi_wide_mst_req, dma_axi_bus)
`AXI_ASSIGN_FROM_RESP(dma_axi_bus, clu_axi_wide_mst_resp)

////////////////////////////////////////////////////////////////////////

chimera_cluster_adapter #(
.WidePassThroughRegionStart(Cfg.MemIslRegionStart),
.WidePassThroughRegionEnd (Cfg.MemIslRegionEnd),
Expand All @@ -182,22 +284,22 @@ module chimera_cluster

) i_cluster_axi_adapter (
.soc_clk_i(soc_clk_i),
.clu_clk_i(clu_clk_i),
// .clu_clk_i(clu_clk_i),
.rst_ni,

.narrow_in_req_i (clu_axi_narrow_slv_req),
.narrow_in_resp_o (clu_axi_narrow_slv_rsp),
.narrow_out_req_o (clu_axi_narrow_mst_req),
.narrow_out_resp_i(clu_axi_narrow_mst_rsp),

.clu_narrow_in_req_o (clu_axi_adapter_slv_req),
.clu_narrow_in_resp_i (clu_axi_adapter_slv_resp),
.clu_narrow_out_req_i (clu_axi_adapter_mst_req),
.clu_narrow_in_req_o (clu_axi_adapter_slv_req), // Cluster side narrow slave
.clu_narrow_in_resp_i (clu_axi_adapter_slv_resp),

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.clu_narrow_out_req_i (clu_axi_adapter_mst_req), // Cluster side narrow master
.clu_narrow_out_resp_o(clu_axi_adapter_mst_resp),

.wide_out_req_o (wide_out_req_o),
.wide_out_resp_i (wide_out_resp_i),
.clu_wide_out_req_i (clu_axi_wide_mst_req),
.clu_wide_out_req_i (clu_axi_wide_mst_req), // Cluster side wide master
.clu_wide_out_resp_o(clu_axi_wide_mst_resp),

.wide_mem_bypass_mode_i(widemem_bypass_i)
Expand All @@ -218,79 +320,122 @@ module chimera_cluster
localparam int unsigned NumIntOutstandingLoads[NrCores] = '{NrCores{32'h1}};
localparam int unsigned NumIntOutstandingMem[NrCores] = '{NrCores{32'h4}};

snitch_cluster #(
.PhysicalAddrWidth(Cfg.AddrWidth),
.NarrowDataWidth (ClusterDataWidth), // SCHEREMO: Convolve needs this...
.WideDataWidth (WideDataWidth),
.NarrowIdWidthIn (ClusterNarrowAxiMstIdWidth),
.WideIdWidthIn (WideMasterIdWidth),
.NarrowUserWidth (Cfg.AxiUserWidth),
.WideUserWidth (Cfg.AxiUserWidth),

.BootAddr(SnitchBootROMRegionStart),

.NrHives (1),
.NrCores (NrCores),
.TCDMDepth (1024),
.ZeroMemorySize (64),
.ClusterPeriphSize(64),
.NrBanks (16),

.DMANumAxInFlight(3),
.DMAReqFifoDepth (3),

.ICacheLineWidth('{256}),
.ICacheLineCount('{16}),
.ICacheSets ('{2}),

.VMSupport(0),
.Xdma ({1'b1, {(NrCores - 1) {1'b0}}}),

.NumIntOutstandingLoads(NumIntOutstandingLoads),
.NumIntOutstandingMem (NumIntOutstandingMem),
.RegisterOffloadReq (1),
.RegisterOffloadRsp (1),
.RegisterCoreReq (1),
.RegisterCoreRsp (1),

.narrow_in_req_t (axi_cluster_in_narrow_req_t),
.narrow_in_resp_t(axi_cluster_in_narrow_resp_t),
.wide_in_req_t (axi_cluster_in_wide_req_t),
.wide_in_resp_t (axi_cluster_in_wide_resp_t),

.narrow_out_req_t (axi_cluster_out_narrow_req_t),
.narrow_out_resp_t(axi_cluster_out_narrow_resp_t),
.wide_out_req_t (axi_cluster_out_wide_req_t),
.wide_out_resp_t (axi_cluster_out_wide_resp_t),

.sram_cfg_t (sram_cfg_t),
.sram_cfgs_t(sram_cfgs_t),

.RegisterExtWide ('0),
.RegisterExtNarrow('0)
) i_test_cluster (

.clk_i (clu_clk_i),
.clk_d2_bypass_i('0),
.rst_ni,

.debug_req_i(debug_req_i),
.meip_i (meip_i),
.mtip_i (mtip_i),
.msip_i (msip_i),

.hart_base_id_i (hart_base_id_i),
.cluster_base_addr_i(cluster_base_addr_i),
.sram_cfgs_i ('0),

.narrow_in_req_i (clu_axi_adapter_slv_req),
.narrow_in_resp_o (clu_axi_adapter_slv_resp),
.narrow_out_req_o (clu_axi_adapter_mst_req),
.narrow_out_resp_i(clu_axi_adapter_mst_resp),
.wide_in_req_i ('0),
.wide_in_resp_o (),
.wide_out_req_o (clu_axi_wide_mst_req),
.wide_out_resp_i (clu_axi_wide_mst_resp)

);
pulp_cluster #(
.NB_CORES ( 8 ), // snitch_cluster had 9 because 1 was DMA

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message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:324 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.HWPE_WIDTH_FAC ( 9 ), // ???
.NB_DMA_PORTS ( 2 ), // ???
.N_HWPE ( 1 ), // ???
.TCDM_SIZE ( 128*1024 ), // ???
.NB_TCDM_BANKS ( 16 ), // ???
.SET_ASSOCIATIVE ( 4 ), // ???
.CACHE_LINE ( 1 ), // ???
.CACHE_SIZE ( 4096 ), // ???
.ICACHE_DATA_WIDTH ( 128 ), // ???
.L0_BUFFER_FEATURE ( "DISABLED" ), // ???
.MULTICAST_FEATURE ( "DISABLED" ), // ???
.SHARED_ICACHE ( "ENABLED" ), // ???
.DIRECT_MAPPED_FEATURE ( "DISABLED" ), // ???
.L2_SIZE ( 32'h10000 ), // ???
.ROM_BOOT_ADDR ( 32'h1A000000 ), // ??? substitute with correct ones

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message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:339 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.BOOT_ADDR ( 32'h1c008080 ), // ??? substitute with correct ones

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message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:340 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.INSTR_RDATA_WIDTH ( 32 ), // ???
.CLUST_FPU ( 1 ),
.CLUST_FP_DIVSQRT ( 1 ),
.CLUST_SHARED_FP ( 2 ),
.CLUST_SHARED_FP_DIVSQRT ( 2 ),
.AXI_ADDR_WIDTH ( Cfg.AddrWidth ),
.AXI_DATA_S2C_WIDTH ( ClusterDataWidth ),
.AXI_DATA_C2S_WIDTH ( ClusterDataWidth ),
.AXI_DMA_DATA_C2S_WIDTH ( WideDataWidth ),
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
.AXI_ID_IN_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_OUT_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_DMA_ID_OUT_WIDTH ( WideMasterIdWidth ),
.LOG_DEPTH ( 3 ),
.DATA_WIDTH ( 32 ), // ???
.ADDR_WIDTH ( 32 ),
.LOG_CLUSTER ( 3 ),
.PE_ROUTING_LSB ( 10 ),
.EVNT_WIDTH ( 8 ),
.IDMA ( 1'b1 ),
.DMA_USE_HWPE_PORT ( 1'b1 )
) cluster_i (
.clk_i ( clu_clk_i ),
.rst_ni ( rst_ni ),
.ref_clk_i ( clu_clk_i ),

.pmu_mem_pwdn_i ( 1'b0 ),

.base_addr_i ( '0 ),

.dma_pe_evt_ack_i ( '1 ),
.dma_pe_evt_valid_o ( ),

.dma_pe_irq_ack_i ( 1'b1 ),
.dma_pe_irq_valid_o ( ),

.dbg_irq_valid_i ( '0 ),

.pf_evt_ack_i ( 1'b1 ),
.pf_evt_valid_o ( ),

.async_cluster_events_wptr_i ( '0 ),
.async_cluster_events_rptr_o ( ),
.async_cluster_events_data_i ( '0 ),

.en_sa_boot_i ( s_cluster_en_sa_boot ), // ??? fix or disconnect

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message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:386 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.test_mode_i ( 1'b0 ), // ??? fix or disconnect

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message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:387 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.fetch_en_i ( s_cluster_fetch_en ), // ??? fix or disconnect

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message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:388 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.eoc_o ( s_cluster_eoc ), // ??? fix or disconnect

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message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:389 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.busy_o ( s_cluster_busy ), // ??? fix or disconnect

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message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:390 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.cluster_id_i ( 6'b000000 ), // ??? fix or disconnect

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[verible-verilog-lint] hw/chimera_cluster.sv#L391 

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message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:391 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

.async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ),
.async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ),
.async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ),
.async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ),
.async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ),
.async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ),
.async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ),
.async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ),
.async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ),
.async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ),
.async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ),
.async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ),
.async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ),
.async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ),
.async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ),

.async_dma_master_aw_wptr_o ( async_dma_axi_bus.aw_wptr ),
.async_dma_master_aw_rptr_i ( async_dma_axi_bus.aw_rptr ),
.async_dma_master_aw_data_o ( async_dma_axi_bus.aw_data ),
.async_dma_master_ar_wptr_o ( async_dma_axi_bus.ar_wptr ),
.async_dma_master_ar_rptr_i ( async_dma_axi_bus.ar_rptr ),
.async_dma_master_ar_data_o ( async_dma_axi_bus.ar_data ),
.async_dma_master_w_data_o ( async_dma_axi_bus.w_data ),
.async_dma_master_w_wptr_o ( async_dma_axi_bus.w_wptr ),
.async_dma_master_w_rptr_i ( async_dma_axi_bus.w_rptr ),
.async_dma_master_r_wptr_i ( async_dma_axi_bus.r_wptr ),
.async_dma_master_r_rptr_o ( async_dma_axi_bus.r_rptr ),
.async_dma_master_r_data_i ( async_dma_axi_bus.r_data ),
.async_dma_master_b_wptr_i ( async_dma_axi_bus.b_wptr ),
.async_dma_master_b_rptr_o ( async_dma_axi_bus.b_rptr ),
.async_dma_master_b_data_i ( async_dma_axi_bus.b_data ),

.async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ),
.async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ),
.async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ),
.async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ),
.async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ),
.async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ),
.async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ),
.async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ),
.async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ),
.async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ),
.async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ),
.async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ),
.async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ),
.async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ),
.async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data )
);
endmodule
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