Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH #1596

dansmathers · 2024-02-07T14:09:48Z

Refresh encoding.h to update CSR_MINTSTATUS, CSR_SINTSTATUS, CSR_UINTSTATUS addresses to read-only csr addresses and add CSR_MINTTHRESH, CSR_SINTTHRESH, CSR_UINTTHRESH csrs.

spec: https://github.com/riscv/riscv-fast-interrupt

Refresh encoding.h to update CSR_MINTSTATUS, CSR_SINTSTATUS, CSR_UINTSTATUS addresses to read-only csr addresses and add CSR_MINTTHRESH, CSR_SINTTHRESH, CSR_UINTTHRESH csrs. spec: https://github.com/riscv/riscv-fast-interrupt Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

aswaterman

encoding.h is an auto-generated file and so shouldn't be edited manually. See the header:

riscv-isa-sim/riscv/encoding.h

Lines 5 to 8 in d4726e1

    
           /* 
        
            * This file is auto-generated by running 'make' in 
        
            * https://github.com/riscv/riscv-opcodes (a014979) 
        
            */

Please make this change in riscv-opcodes and, after that PR is merged, regenerate encoding.h and copy it over to here.

dansmathers · 2024-02-08T16:05:48Z

created riscv/riscv-opcodes#226

closing pull until riscv-opcodes PR is merged.

This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

aswaterman requested changes Feb 7, 2024

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dansmathers closed this Feb 8, 2024

dansmathers mentioned this pull request Feb 9, 2024

Draft: Add m-mode, s-mode CLIC interrupt testcases riscv-non-isa/riscv-arch-test#436

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This was referenced Mar 1, 2024

Add unratified Smclic, Ssclic, Smclicshv extensions riscv/sail-riscv#420

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SAIL implementation of CLIC riscv/riscv-fast-interrupt#185

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Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH #1596

Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH #1596

dansmathers commented Feb 7, 2024

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dansmathers commented Feb 8, 2024

	/*
	* This file is auto-generated by running 'make' in
	* https://github.com/riscv/riscv-opcodes (a014979)
	*/

Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH #1596

Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH #1596

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dansmathers commented Feb 8, 2024