Add B extension #385
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Add B extension #385
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jrtc27
reviewed
Jan 7, 2024
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Yes, that's why Zmmul and M can both be set. Clearing misa.M is then just
removing the DIV/REM instructions but not the MUL instructions.
I don't know why anyone would ever do that, but mine is not to reason
why....
…On Sun, Jan 7, 2024 at 1:41 PM Ved Shanbhogue ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In model/riscv_insts_zba.sail
<#385 (comment)>:
> @@ -71,8 +71,8 @@
/* ****************************************************************** */
union clause ast = RISCV_SLLIUW : (bits(6), regidx, regidx)
-mapping clause encdec = RISCV_SLLIUW(shamt, rs1, rd) if haveZba() & sizeof(xlen) == 64
- <-> 0b000010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011 if haveZba() & sizeof(xlen) == 64
+mapping clause encdec = RISCV_SLLIUW(shamt, rs1, rd) if (haveZba() | haveBExt()) & sizeof(xlen) == 64
But that not allow expressing behavior of clearing B clearly. For
instance, if misa.B and haveZba was both 1 at reset. Then clearing B would
leave Zba available. But if misa.B was 1 and haveZba was 0 at reset then
clearing B would disable Zba. Forcing state of Zba to misa.B would not
allow expressing this.
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jrtc27
reviewed
Jan 11, 2024
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@billmcspadden-riscv this spec was recently ratified, can this be merged? |
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Does the |
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Please see the conversation thread in this PR. |
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I'll merge this in a couple of days if nobody objects. @ved-rivos what would you say your highest priority PR is? I think it would be good to get some more merged if possible. |
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Specification: https://github.com/riscv/riscv-b