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Implement Zicbom, Zicboz (cbo.flush, cbo.inval, cbo.zero) #455

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merged 1 commit into from
Aug 30, 2024

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Timmmm
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@Timmmm Timmmm commented Apr 22, 2024

Note that Zicbop (prefetch hints) does not need to be implemented because all it does is label some existing base instructions as prefetch hints.

Also I have not wired up the enable flags to the emulators because it is rather tedious (and will hopefully be replaced by riscv-config at some point).

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github-actions bot commented Apr 22, 2024

Test Results

712 tests  ±0   712 ✅ ±0   0s ⏱️ ±0s
  6 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit fcd31da. ± Comparison against base commit 05b845c.

♻️ This comment has been updated with latest results.

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@bacam
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bacam commented Apr 22, 2024

Note that Zicbop (prefetch hints) does not need to be implemented because all it does is label some existing base instructions as prefetch hints.

Shouldn't there be encoding and assembly information at least? It might also be useful to calculate the address and pass it to a built-in function so that it could be logged (e.g., to check that some code's prefetch instruction refers to the correct address), along with a comment noting that no exceptions are taken if something goes wrong.

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Timmmm commented Apr 23, 2024

Shouldn't there be encoding and assembly information at least? It might also be useful to calculate the address and pass it to a built-in function so that it could be logged (e.g., to check that some code's prefetch instruction refers to the correct address), along with a comment noting that no exceptions are taken if something goes wrong.

That's a good point... I think it can be a separate PR though if anyone wants to tackle it.

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HI,
Just wanted to check, Is this the main PR for cbo.zero support in sail? and Can anyone please let me know, if there's an ETA to close this.

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Timmmm commented Jul 16, 2024

Yes it is - it's based on the older one (#137) with some fixes. As far as I am concerned it is ready to merge; it's just waiting on review.

No ETA I'm afraid - not many people are actively reviewing PRs and unfortunately nobody is paid to do it currently. (IMO RVI should hire someone to do this but that's an ongoing discussion.)

@billmcspadden-riscv
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billmcspadden-riscv commented Jul 16, 2024 via email

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billmcspadden-riscv commented Jul 16, 2024 via email

@Timmmm
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Timmmm commented Jul 16, 2024

Thanks, I've rebased and fixed the conflicts.

It's been tested by running against our A730 chip with the following tests:

  • cbo.zero-01.S from riscv-arch-test
  • zero.S from riscv-tests
  • A very basic directed test we wrote that does some stores and loads combined with the CBO instructions and CSR settings.
  • STING - it's not really clear exactly what they test (the descriptions are unhelpfully short like "Test for cmo instruction - CBO.FLUSH") but they're generally pretty good.

The first two only test cbo.zero; I'm not sure why they didn't add tests for the other instructions.

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billmcspadden-riscv commented Jul 16, 2024 via email

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Timmmm commented Jul 16, 2024

Thanks for the review @jrtc27 !

@animesh211
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HI, It'll be great if this can be reviewed and closed.

@Timmmm Timmmm force-pushed the user/timh/cbo branch 2 times, most recently from 69e993b to c0729fb Compare August 5, 2024 14:38
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aprnath commented Aug 15, 2024

Adding a gentle nudge to animesh211's request for this to be merged and closed.

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Note that Zicbop (prefetch hints) does not need to be implemented because all it does is label some existing base instructions as prefetch hints.
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Timmmm commented Aug 29, 2024

I rebased this and updated it to use the new extensionEnabled() function. Arguably this:

function clause extensionEnabled(Ext_Zicbom) = sys_enable_zicbom()

should be this

function clause extensionEnabled(Ext_Zicbom) = sys_enable_zicbom() & cbo_zero_enabled(cur_privilege)

however I left it as it was just so we can get this in.

@billmcspadden-riscv any objection to merging this? I think it has been ready with no objections for a long time.

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LGTM

@billmcspadden-riscv billmcspadden-riscv merged commit e199a2e into riscv:master Aug 30, 2024
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Timmmm commented Aug 30, 2024

Thanks!

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7 participants