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west.yml: update zephyr to b2f7ea0523 #8268

Merged
merged 5 commits into from
Sep 28, 2023
Merged

west.yml: update zephyr to b2f7ea0523 #8268

merged 5 commits into from
Sep 28, 2023

Commits on Sep 26, 2023

  1. platform: posix: clk: add lowest freq index 

    This patch adds CPU_LOWEST_FREQ_IDX definition to keep compliance with
changes in base_fw.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Sep 26, 2023
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  2. base_fw: get fw config 

    This patch is changing value of slow clock in response for FwConfigGet
from LP clock to the lowest clock is section "slow clock".

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Sep 26, 2023
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  3. ace: clock: update clock definitions 

    ACE_1.5 and ACE_2.0 use only two clocks for DSP cores. First is WOVRCO and
second is ACE IPLL.

IPLL allows to configure it to work like LP RING Oscillator Clock or HP
RING Oscillator Clock. Currently, the driver does not allow this, so I
remove the frequency that cannot be achieved anyway.

Clocks frequencies:
WOV: 38.4 MHz
IPLL: 393.216 MHz

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Sep 26, 2023
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  4. ace: overlay: update clock frequency 

    Changing max clock frequency for FPGA configuration.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Sep 26, 2023
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  5. west.yml: update zephyr to b2f7ea0523 

    Zepych update: total of 736 commits.

492517b918 west.yml: Update NXP HAL SDK to 2.14
a5d1fd9857 soc: adsp: clk: update clock switch flow
9656056b19 dts: adsp: ace20: remove lp clock
50f0e223e8 dts: adsp: ace15: remove lp clock
cf6d5f95b6 adsp: clk: ace: select ipll if wovrco is unavailable
2d835e1b29 dts: adsp: ace20: replace hp with ipll clock
dcecda859c dts: adsp: ace15: replace hp with ipll clock
2f2689e3d3 intel_adsp: ace15: shim: update wovrco request bit
ea9dd59460 yamllint: bindings: add ipll clock index
1ddabfa8d8 dai: intel: dmic: fix shadow variable
b26921d776 dai: intel: dmic: New functions for writing fir coefficients
cba9ec10c3 dai: intel: tgl: dmic: Refactor of dai_nhlt_dmic_dai_params_get function
c28e8ba9ba dai: intel: dmic: Add pdm_base and pdm_idx variables in blob parser
2452aaad50 dai: intel: dmic: Separate fir configuration code into function
f74fd8edaf dai: intel: ace: dmic: Add dai_dmic_start_fifo_packers function
76d03e798f dai: intel: ace: dmic: Using the WAIT_FOR macro in waiting functions
3fbaed4de9 dai: intel: ace: dmic: Refactor of dai_nhlt_dmic_dai_params_get function
d7672af838 dai: intel: dmic: Combine PDM registers definitions
8ea53d49b6 dai: intel: dmic: nhlt: Move debug print code to a separate functions
81944c5c62 dai: intel: dmic: Move definitions of nhlt structures to a new file

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Sep 26, 2023
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