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west.yml: update zephyr to b2f7ea0523 #8268

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1 change: 1 addition & 0 deletions app/overlays/lnl/fpga_overlay.conf
Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
CONFIG_DAI_DMIC_HW_IOCLK=19200000
CONFIG_XTENSA_CCOUNT_HZ=40000000
1 change: 1 addition & 0 deletions app/overlays/mtl/fpga_overlay.conf
Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
CONFIG_DAI_DMIC_HW_IOCLK=19200000
CONFIG_XTENSA_CCOUNT_HZ=40000000
2 changes: 1 addition & 1 deletion src/audio/base_fw.c
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ static int basefw_config(uint32_t *data_offset, char *data)
tuple = tlv_next(tuple);
tlv_value_uint32_set(tuple,
IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG,
clock_get_freq(CPU_LPRO_FREQ_IDX));
clock_get_freq(CPU_LOWEST_FREQ_IDX));

tuple = tlv_next(tuple);
tlv_value_uint32_set(tuple, IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG, IPC4_ALH_CAVS_1_8);
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10 changes: 4 additions & 6 deletions src/platform/lunarlake/include/platform/lib/clk.h
Original file line number Diff line number Diff line change
Expand Up @@ -14,21 +14,19 @@

#include <ace/lib/clk.h>

#define CLK_MAX_CPU_HZ 400000000
#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ

#define CPU_WOVCRO_FREQ_IDX 0

#define CPU_LPRO_FREQ_IDX 1

#define CPU_HPRO_FREQ_IDX 2
#define CPU_IPLL_FREQ_IDX 1

#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX

#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX
#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX

#define SSP_DEFAULT_IDX 1

#define NUM_CPU_FREQ 3
#define NUM_CPU_FREQ 2

#define NUM_SSP_FREQ 3

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5 changes: 2 additions & 3 deletions src/platform/lunarlake/lib/clk.c
Original file line number Diff line number Diff line change
Expand Up @@ -9,9 +9,8 @@
#include <rtos/clk.h>

static const struct freq_table platform_cpu_freq[] = {
{ 38400000, 38400 },
{ 120000000, 120000 },
{ CLK_MAX_CPU_HZ, 400000 },
{ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 },
{ CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 },
};

STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies);
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10 changes: 4 additions & 6 deletions src/platform/meteorlake/include/platform/lib/clk.h
Original file line number Diff line number Diff line change
Expand Up @@ -14,21 +14,19 @@

#include <ace/lib/clk.h>

#define CLK_MAX_CPU_HZ 400000000
#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ

#define CPU_WOVCRO_FREQ_IDX 0

#define CPU_LPRO_FREQ_IDX 1

#define CPU_HPRO_FREQ_IDX 2
#define CPU_IPLL_FREQ_IDX 1

#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX

#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX
#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX

#define SSP_DEFAULT_IDX 1

#define NUM_CPU_FREQ 3
#define NUM_CPU_FREQ 2

#define NUM_SSP_FREQ 3

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5 changes: 2 additions & 3 deletions src/platform/meteorlake/lib/clk.c
Original file line number Diff line number Diff line change
Expand Up @@ -9,9 +9,8 @@
#include <rtos/clk.h>

static const struct freq_table platform_cpu_freq[] = {
{ 38400000, 38400 },
{ 120000000, 120000 },
{ CLK_MAX_CPU_HZ, 400000 },
{ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 },
{ CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 },
};

STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies);
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1 change: 1 addition & 0 deletions src/platform/posix/include/platform/lib/clk.h
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@

#define CLK_MAX_CPU_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#define CPU_LPRO_FREQ_IDX 1
#define CPU_LOWEST_FREQ_IDX CPU_LPRO_FREQ_IDX

/* This is not a platform function, it's defined in src/lib/clk.c.
* But the declaration has historically been in the platform layer, so
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2 changes: 1 addition & 1 deletion west.yml
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ manifest:

- name: zephyr
repo-path: zephyr
revision: 2f90ef488a4e97c94c2cc5b95dacd1b15de32216
revision: 492517b918d267f553688cd6b9d59b92ffc10f91
remote: zephyrproject

# Import some projects listed in zephyr/west.yml@revision
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