All the projects and assignments done as part of VLSI course.

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

work done as part of VLSI Design practice course

Digital System Design Lab Codes using Verilog

explore different implementations of adders and study their characteristics.

Parametrized Verilog implementation of different architectures of adder / subtractor circuits.

Progetto di Elettronica Digitale AA 2022-2023

Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.

An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

My VHDL Codes during EE214 (Digital Lab) Spring 2020-21

All the various adders in Verilog!

A repository for some modules I made while learning Verilog

Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.

Computer Architecture - Practical Solution with Quartus - Sharif University of Technology

Implementation of four Ripple-Carry Quantum Adders with Qiskit.

This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.

A 4-bit ripple-carry adder-subtractor created in Logisim.

designed simple digital circuits using verilog

Useful VHDL scripts for hardware description.